The structural and electrical properties of the SrTa2O6/In0.53Ga0.47As/InP system

The structural and electrical properties of SrTa₂O₆(SrTaO)/n-In_0.53GaAs_0.47(InGaAs)/InP structures where the SrTaO was grown by atomic vapor deposition, were investigated. Transmission electron microscopy revealed a uniform, amorphous SrTaO film having an atomically flat interface with the InGaAs substrate with a SrTaO film thickness of 11.2 nm. The amorphous SrTaO films (11.2 nm) exhibit a dielectric constant of ∼20, and a breakdown field of >8 MV/cm. A capacitance equivalent thickness of ∼1 nm is obtained for a SrTaO thickness of 3.4 nm, demonstrating the scaling potential of the SrTaO/InGaAs MOS system. Thinner SrTaO films (3.4 nm) exhibited increased non-uniformity in thickness. From the capacitance-voltage response of the SrTaO (3.4 nm)/n-InGaAs/InP structure, prior to any post deposition annealing, a peak interface state density of ∼2.3 × 10¹³ cm⁻² eV⁻¹ is obtained located at ∼0.28 eV (±0.05 eV) above the valence band energy (E_v) and the integrated interface state density in range E_v + 0.2 to E_v + 0.7 eV is 6.8 × 10¹² cm⁻². The peak energy position (0.28 ± 0.05 eV) and the energy distribution of the interface states are similar to other high-k layers on InGaAs, such as Al₂O₃ and LaAlO₃, providing further evidence that the interface defects in the high-k/InGaAs system are intrinsic defects related to the InGaAs surface.     

SrO capping effect for La2O3/Ce-silicate gate dielectrics

The chemical bonding states and electrical characteristics of SrO capped La₂O₃/CeO_x gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5 nm has been demonstrated. A strongly degraded effective electron mobility of 78 cm²/V s at 1 MV/cm has been obtained, which fit well with the general trend in small EOT range below 1 nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling.     

Characteristics of metal-oxide-semiconductor (MOS) device with Er metal gate on SiO2 film

We have investigated the structural and electrical properties of metal-oxide-semiconductor (MOS) devices with Er metal gate on SiO₂ film. Rapid thermal annealing (RTA) process leads to the formation of a high-k Er-silicate gate dielectric. The in situ high-voltage electron microscopy (HVEM) results show that thermally driven Er diffusion is responsible for the decrease in equivalent oxide thickness (EOT) with an increase in annealing temperature. The effective work function (Φ_m,eff) of Er metal gate, extracted from the relations of EOT versus flat-band voltage (V_FB), is calculated to be ∼2.86 eV.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

A novel thermally-stable zirconium amidinate ALD precursor for ZrO2 thin films

ZrO₂ thin films were deposited by the atomic layer deposition process on Si substrates using tetrakis(N,N′-dimethylacetamidinate) zirconium (Zr-AMD) as a Zr precursor and H₂O as an oxidizing agent. Tetrakis (ethylmethylamino) zirconium (TEMA-Zr) was also evaluated for a comparative study. Physical properties of ALD-derived ZrO₂ thin films were studied using ellipsometry, grazing incidence XRD (GI-XRD), high resolution TEM (HRTEM), and atomic force microscopy (AFM). The ZrO₂ deposited using Zr-AMD showed a better thermal stability at high substrate temperature (>300 °C) compared to that using TEMA-Zr. GI-XRD analysis reveals that after 700 °C anneal both ZrO₂ films enter tetragonal phase. The electrical properties of N₂-annealed ZrO₂ film using Zr-AMD exhibit an EOT of 1.2 nm with leakage current density as low as 2 × 10⁻³ A/cm² (@V_fb−1 V). The new Zr amidinate is a promising ALD precursor for high-k dielectric applications.     

Self-aligned n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using HfO2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO₂/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm²/V s) with high temperature PMA (950 °C, 1 min) and good inversion.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

Properties of ALD HfTaxOy high-k layers deposited on chemical silicon oxide

HfTa_xO_y high-k dielectric layers with different compositions were deposited using ALD on 1 nm SiO₂ generated by ozone based cleaning of 200 mm Si(1 0 0) surface. Physical characterization of blanket layers and C-V mapping demonstrates that the ALD layers have excellent uniformity and controllable compositions. The layers with a composition of HfTaO_5.5 remain amorphous after annealing at 900 °C. The C-V measurements of MOS capacitors show no hysteresis, negligible frequency dispersion and interfacial state density smaller than 3 × 10¹¹ (cm⁻² eV⁻¹). k-value of the amorphous layers varies in the range from 20 to 25, depending on layer composition. The flat band voltage does not shift with the increase of EOT, implying that the effect of fixed charge densities in the layers is negligible. The I-V measurements show a leakage reduction comparable to that of the ALD HfO₂ layers.     

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors

The HfO₂ high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO₂ thin films with 9.45 nm thickness have been used for Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current-voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10¹⁰, 9.25 × 10¹¹ cm⁻² eV⁻¹ and 9.12 × 10⁻⁶ A/cm² respectively for annealed HfO₂ thin films.     

Electrical characteristics and reliability properties of metal-oxide-semiconductor capacitors with HfZrLaO gate dielectrics

Metal-oxide-semiconductor (MOS) capacitors incorporating atomic-layer-deposition (ALD) HfZrLaO high-κ gate dielectric were fabricated and investigated. The equivalent oxide thickness (EOT) is 0.68 nm and the gate leakage current density (J_g) is only 9.3 × 10⁻¹ A/cm². The time-dependence dielectric breakdown (TDDB) behavior agrees with the percolation model, and the TDDB characteristics are consistent with the thermochemical E-model for lifetime projection. The experimental results show that the Weibull slopes are almost independent of capacitor area and stress conditions. The field acceleration parameter (γ) and activation energy (ΔH₀) are determined around 5.9-7.0 cm/MV and 0.54-0.60 eV, respectively. At 85 °C, the maximum voltage projected for 10-years TDDB lifetime is 1.87 V.     

Improvement on low-temperature deposited HfO2 film and interfacial layer by high-pressure oxygen treatment

In this study, high-pressure oxygen (O₂ and O₂ + UV light) technologies were employed to effectively improve the properties of low-temperature-deposited metal oxide dielectric films and interfacial layer. In this work, 13 nm HfO₂ thin films were deposited by sputtering method at room temperature. Then, the oxygen treatments with a high-pressure of 1500 psi at 150 °C were performed to replace the conventional high temperature annealing. According to the XPS analyses, integration area of the absorption peaks of O-Hf and O-Hf-Si bonding energies apparently raise and the quantity of oxygen in deposited thin films also increases from XPS measurement. In addition, the leakage current density of standard HfO₂ film after O₂ and O₂ + UV light treatments can be improved from 3.12 × 10⁻⁶ A/cm² to 6.27 × 10⁻⁷ and 1.3 × 10⁻⁸ A/cm² at |Vg| = 3 V. The proposed low-temperature and high pressure O₂ or O₂ + UV light treatment for improving high-k dielectric films is applicable for the future flexible electronics.     

High performance TaYOx-based MIM capacitors

TaYO_x-based metal-insulator-metal (MIM) capacitors with excellent electrical properties have been fabricated. Ultra-thin TaYO_x films in the thickness range of 15-30 nm (EOT ∼ 2.4-4.7 nm) were deposited on Au/SiO₂ (100 nm)/Si (100) structures by rf-magnetron co-sputtering of Ta₂O₅ and Y₂O₃ targets. TaYO_x layers were characterized by X-ray photoelectron spectroscopy (XPS), energy dispersive X-ray (EDX) and X-ray diffraction (XRD) to examine the composition and crystallinity. An atomic percentage of Ta:Y = 58.32:41.67 was confirmed from the EDX analysis while XRD revealed an amorphous phase (up to 500 °C) during rapid thermal annealing. Besides, a high capacitance density of ∼3.7-5.4 fF/μm² at 10 kHz (ε_r ∼ 21), a low value of VCC (voltage coefficients of capacitance, α and β) have been achieved. Also, a highly stable temperature coefficient of capacitance, TCC has been obtained. Capacitance degradation phenomena in TaYO_x-based MIM capacitors under constant current stressing (CCS at 20 nA) have been studied. It is observed that degradation depends strongly on the dielectric thickness and a dielectric breakdown voltage of 3-5 MV/cm was found for TaYO_x films. The maximum energy storage density was estimated to be ∼5.69 J/cm³. Post deposition annealing (PDA) in O₂ ambient at 400 °C has been performed and further improvement in device reliability and electrical performances has been achieved.     

Pentacene thin-film transistors with sol-gel derived amorphous Ba0.6Sr0.4TiO3 gate dielectric

An amorphous Ba_0.6Sr_0.4TiO₃ (BST) film with the thickness of 200 nm was deposited on indium-tin-oxide (ITO)-coated glass substrate through sol-gel route and post-annealing at 500 °C. The dielectric constant of the BST film was determined to be 20.6 at 100 kHz by measuring the Ag/BST/ITO parallel plate capacitor, and no dielectric tunability was observed with the bias voltage varying from −5 to 5 V. The BST film shows a dense and uniform microstructure as well as a smooth surface with the root-mean-square (RMS) roughness of about 1.4 nm. The leakage current density was found to be 3.5 × 10⁻⁸ A/cm² at an applied voltage of −5 V. The transmittance of the BST/ITO/glass structure is more than 70% in the visible region. Pentacene based transistor using the as-prepared BST film as gate insulator exhibits a low threshold voltage of −1.3 V, the saturation field-effect mobility of 0.68 cm²/Vs, and the current on/off ratio of 3.6 × 10⁵. The results indicate that the sol-gel derived BST film is a promising high-k gate dielectric for large-area transparent organic transistor arrays on glass substrate.     

Trap parameters and conduction mechanism in HfO2-Ta2O5 mixed stacks in response to microwave irradiation

The effect of microwave treatment at room temperature on the leakage current and mechanisms of conductivity in mixed HfO₂-Ta₂O₅ (10 nm) stacks has been studied by temperature dependent (20-100 °C) current-voltage characteristics. It was established that the short term irradiation (∼6 s) affects the electrically active centers in the mixed oxide, provokes modification of the dominant conduction mechanism at about and above 1 MV/cm and improves the temperature stability of capacitors manifesting as low level of current at high temperatures (current decrease up to two orders of magnitude at 100 °C after the treatment is detected). The traps involved in the conduction processes in pre- and post-irradiation capacitors are identified. The longer exposure (10-15 s) is effective in a significant reduction of leakage current (up to 3-4 orders of magnitude in wide range of applied voltages). The potential of microwave treatment at room temperature as technological step for improving the temperature stability of leakage current in high-k stacked capacitors is discussed.     

Effect of RuO2 electrode on laser-MBE prepared HfO2 gate dielectrics

In this paper, we report our recent study of the effect of RuO₂ as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO₂, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO₂ for pMOS devices. Structural, dielectric and electric properties were investigated. RuO₂/HfO₂/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm⁻¹). Compared to the SiO₂ dielectric with the same EOT value, RuO₂/HfO₂/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO₂ top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 10¹² cm⁻². All the results above indicate that RuO₂ is a promising alternative gate electrode for LMBE grown HfO₂ gate dielectrics.     

Selection of rare earth silicates for highly scaled gate dielectrics

An aggressive equivalent oxide thickness (EOT) scaling with high-k gate dielectrics has been demonstrated by ultra-thin La₂O₃ gate dielectric with a proper selection of rare earth (La-, Ce- and Pr-) silicates as an interfacial layer. Among silicates, Ce-silicate has shown the lowest interface-state density as low as 10¹¹ cmv⁻²/eV with a high dielectric constant over 20. n-Type field-effect transistor (FET) with a small EOT of 0.51 nm has been successfully fabricated with a La₂O₃ gate dielectric on a Ce-silicate interfacial layer after annealing at 500 °C. Negative shift in threshold voltage and reduced effective electron mobility has indicated the presence of fixed charges in the dielectric. Nonetheless, the high dielectric constant and nice interfacial property of Ce-silicate can be advantageous for the interfacial layer in highly scaled gate dielectrics.     

Measurement of As diffusivity in Ni2Si thin films

The lattice and grain boundary diffusion coefficients of As in 260 nm-thick Ni₂Si films were measured. The Ni₂Si layers were prepared via the reaction between a Si layer deposited by low pressure chemical vapor deposition and a Ni layer deposited by magnetron sputtering on a Si substrate covered with a SiO₂ film. As was implanted in the silicide. Its concentration profiles were measured using secondary ion mass spectroscopy before and after annealing (550-700 °C). 2D finite element diffusion simulations taking into account lattice diffusion and grain boundary (GB) diffusion were performed based on the microstructure of the samples. They were found to fit accurately the measured profiles and allowed to measure the diffusion coefficients for each temperature. Lattice diffusion is characterized by a pre-exponential factor D⁰v ∼ 1.5 × 10⁻¹ cm² s⁻¹ and an activation energy Qv ∼ 2.72 eV. In the case of GB diffusion P⁰ = sδD⁰gb = 9.0 × 10⁻³ cm³ s⁻¹ and the activation energy was found to be higher than for lattice diffusion with Qgb ∼ 3.07 eV. Existing data concerning diffusion in silicides and other materials is used to discuss these results. The diffusion of As in Ni₂Si could be reduced due to impurity segregation in GBs.     

Ferroelectric and leakage current characteristics of (Pb0.72La0.28)Ti0.93O3 thin films prepared by a sol-gel process

(Pb_1 − xLa_x)Ti_1 − x/4O₃(x = 28 mol%, denoted as PLT) thin films were grown on Pt/Ti/SiO₂/Si substrates by using a sol-gel process. The Pt/PLT/Pt film capacitor showed well-saturated hysteresis loops at an applied electric field of 500 kV/cm with spontaneous polarization (P_s), remanent polarization (P_r) and coercive electric field (E_c) values of 9.23 μC/cm², 0.53 μC/cm² and 19.7 kV/cm, respectively. At 100 kHz, the dielectric constant and dissipation factor of the film were 748 and 0.026, respectively. The leakage current density is lower than 1.0 × 10⁻⁷ A/cm²over the electric field range of 0 to 200 kV/cm. And the Pt/PLT interface exist a Schottky emission characteristics.     

Interface state densities, low frequency noise and electron mobility in surface channel In0.53Ga0.47As n-MOSFETs with a ZrO2 gate dielectric

This paper reports on an investigation of interface state densities, low frequency noise and electron mobility in surface channel In_0.53Ga_0.47As n-MOSFETs with a ZrO₂ gate dielectric. Interface state density values of D_it ∼ 5 × 10¹² cm⁻² eV⁻¹ were extracted using sub-threshold slope analysis and charge pumping technique. The same order of magnitude of trap density was found from low frequency noise measurements. A peak effective electron mobility of 1200 cm²/Vs has been achieved. For these surface channel In_0.53Ga_0.47As n-MOSFETs, it was found that η parameter, an empirical parameter used to calculate the effective electric field, was ∼0.55, and is to be comparable to the standard value found in Si device.