Evaluation of the full operational cycle of a CMOS transfer-gated photodiode active pixel

In this paper we evaluate the full operational cycle of the active-pixel circuit for CMOS image sensors in which four field-effect transistors are suitably combined with an ordinary photodiode; meaning a vertical p–n junction, as opposed to photogates, and with no custom pinned layer. Although this circuit topology itself is not novel, this evaluation intends to shine new light on the use of regular photodiodes. They became largely in disuse in four-transistor image chips under earlier process and design circumstances because the fourth transfer-gate FET did not hold a constant signal long enough and not for a fixed time. Our aim is to investigate the full underlying operational regimen of the transfer gate to propose that a regular photodiode might again be a choice to consider in the four-transistor pixel configuration, not only in conventional imaging but also in dedicated optical applications. The use of an ordinary p–n junction photodiode is advantageous as it offers full compatibility with even elementary mainstream CMOS processes. This investigation resorts to experiments and models both with fabricated integrated pixels and with a macro-pixel circuit implementation.     

激光单条扫描定域再结晶SOI技术研究

本文描述了用于制作三维集成电路（３Ｄ－ＩＣ）的激光再结晶工艺的实验装置和工艺过程，报道了反射条结构样品的单条扫描定域再结晶的实验结果并作了相应的讨论，实验表明，再结晶质量与激光功率、预热温度、高反区条宽以及激光扫描速率等因素有关，并受到工艺稳定性的影响；利用激光单条扫描定域再结晶技术已获得１２ｕｍ宽度、芯片长度的能用以制作高性能ＭＯＳＦＥＴ的ＳＯＩ单晶条。     

CMOS集成电路低功耗设计方法

近年来，功耗问题已成为VLSI设计，尤其是在电池供电的应用中必须考虑的重要问题之一。文章通过对CMOS集成电路功耗起因的分析，对CMOS集成电路低功耗设计方法和设计工具进行了深入的讨论。     

SOI技术的机遇和挑战

本文较为系统地描述了SOI技术的特点,分析了SOI技术中存在的问题和发展的潜力,最后得出了SOI技术将在特征尺寸小于0．1um,电源电压小于1V的新一代集成电路技术中得到了广泛应用。     

A high precision temperature control system for CMOS integrated wide range resistive gas sensors

In this work we present an integrated interface for wide range resistive gas sensors able to heat the sensor resistance through a constant power heater block at 0°C–350°C operating temperatures. The proposed temperature control system is formed by a sensor heater (which fixes the sensor temperature at about 200°C), a R/f (or R/T) converter, which converts the resistive value into a period (or frequency), and can be able to reveal about 6 decades variation (from 10 KΩ up to 10 GΩ), and a digital subsystem that control the whole systems loop. This interface allows high sensibility and precision and performs good stability in temperature and power supply drift and low power characteristics so it can be used also in portable applications. Test measurements, performed on the fabricated chip, have shown an excellent agreement between theoretical expectations and simulation results. Giuseppe Ferri is an associate professor in Electronics at the Department of Electrical Engineering of L’ Aquila University, Ital. In 1993 he has been a visiting researcher at SGS-Thomson Milano, working in bipolar low-voltage op-amp design. In 1994-95 he has been visiting researcher at KU Leuven working in low-voltage CMOS design in the group of Prof. Sansen. His research activity is actually centred on the analog design of integrated circuits for portable applications (e.g., sensors and biomedicals) and circuit theory. He is co-author of a book entitled “Low Voltage, Low Power CMOS Current Conveyors”, Kluwer ed. (2003) and four text-books in Italian on Analogue Microelectronics (2005, 2006). Moreover, he is author and co-author of 74 papers on international and Italian journals and 123 talks at national and international conferences. Vincenzo Stornelli was born in Avezzano (AQ), Italy, on May 31, 1980. He received the Electronics Engineering degree (cum laude) in July 2004. In October 2004 he joined the Department of Electronic Engineering, University of L’Aquila, where he is actually involved with problems concerning project and design of integrated circuits for RF and sensor applications, CAD modelling, characterization, and design analysis of active microwave components, circuits, and subsystems. He regularly teaches courses of the European Computer patent and has regular collaborations with national corporations such as Thales Italia     

TRANSIENT CHARACTERISTIC ANALYSIS OF HIGH TEMPERATURE CMOS DIGITAL INTEGRATED CIRCUITS

This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.     

SOI CMOS模拟集成电路发展概述

从SOI CMOS模拟集成电路(IC)中存在的关键问题——浮体效应——及其影响出发，介绍了在解决浮体效应以后，已实现的有代表性的模拟集成电路的发展状况。特别指出了SOI CMOS在实现RF电路及SOC芯片中的优点。     

一种高稳定低功耗CMOS过热保护电路的设计

采用1．2μm CMOS工艺,设计了一种过热保护电路,并利用Cadence Spectre仿真工具对电路进行了仿真,结果表明,电路的输出信号对电源的抑制能力很强,在3．5V以上的电源电压工作下,输出过热保护信号所产生的过热温度点基本保持不变,约为132℃;同时在3V电源电压工作下,电路功耗约为1．05mW,而在9V的高压下工作,功耗仅为14．4mW。由此可见,此电路性能较好,可广泛应用在各种集成电路内部。     

Substrate noise isolation improvement in a single-well standard CMOS process

This work describes a fully CMOS compatible methodology, which makes available a pseudo deep n-well in single-well standard CMOS process. The proposed method is based on mask manipulation to accommodate the field implant p-type region into the n-well, and does not require any additional masks or modification in the CMOS process flow. According to the experimental results, the floating NMOS made available by the methodology shows a reduction in the threshold voltage, which implies a slight improvement in its performance, when compared with its standard NMOS counterpart. It was also experimentally demonstrated up to 3 GHz, that the guard-ring field implant/pseudo deep n-well proposed structure improves substrate noise isolation when compared to the classical p+ guard-ring, with a maximum improvement above 20 dB for low frequencies and a minimum of 4 dB at 3 GHz.     

CMOS异或电路的设计与应用

设计了四种CMOS"异或"单元电路,通过模拟仿真分析了它们各自的性能特点,并讨论了它们在奇偶检测电路、微处理器系统加法器电路以及单片机全加电路等设计中的不同应用.     

CMOS可预置双边沿触发器的设计及其应用

本文从消除时钟信号冗余跳变而致的无效功耗的要求出发,提出一种基于CMOS传输门的双边沿触发器设计,并设置了它的直接预置控制端以使达到实用的要求。该触发器已用PSPICE程序模拟验证了具有完整的功能。使用该触发器设计时序系统的实例被演示。对模拟所得数据的计算结果表明,与采用相同功能的单边沿触发器的系统比较,由于工作频率减半可使采用双边沿触发器的系统功耗明显降低。     

Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 m CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.     

Uncalibrated automatic bridge-based CMOS integrated interfaces for wide-range resistive sensors portable applications

In this work the authors describe improved solutions on automatic fully-analog uncalibrated Wheatstone bridge-based interfaces suitable for wide-range resistive sensors. The proposed topologies are enhanced and integrated interfaces, based on automatic bridge configurations, completely designed in a standard CMOS technology (AMS 0.35 μm), where Voltage Controlled Resistors (VCRs), formed by MOS transistors, have been properly tuned through the use of a suitable closed feedback loop that continuously ensures the bridge equilibrium condition. The microelectronic design has been performed through the use of symmetrical Operational Transconductance Amplifiers (OTAs) with low-voltage (2 V, single supply) and low-power (63.5 μW) characteristics, so the overall system can be fabricated in a single chip suitable for portable applications. Referring to the first configuration where only one VCR has been employed for both grounded and floating resistive sensors, Orcad PSpice simulations have confirmed the interface capability to estimate the sensor resistance for about 2.7 decades variations (430 Ω; 220 kΩ), with a relative error of about ±4%. Moreover, in the second version for an extended estimation range, the interface is able to evaluate the sensor resistance for about 6.6 decades (0.1 Ω; 400 kΩ) with a reduced relative error within (−1.5%; +4%).     

电流型CMOS脉冲D触发器设计

该文根据脉冲触发器的设计要求,结合阈算术代数系统,提出一种电流型CMOS脉冲D触发器的通用结构,用于二值及多值电流型CMOS脉冲触发器的设计,并可方便地应用于单边沿和双边沿触发。在此结构的基础上设计了电流型CMOS二值、三值以及四值脉冲D触发器。采用TSMC 180 nm CMOS工艺参数对所设计的电路进行HSPICE模拟后表明所设计的电路具有正确的逻辑功能和良好的瞬态特性,且较以往文献提出的电流型D触发器,优化了触发器的建立时间和保持时间,二值和四值触发器最差最小D-Q延时比相关文献的主从触发器降低了59.67%和54.99%,比相关文献的边沿触发器降低了4.62%以上,所用晶体管数也相对减少,具有更简单的结构以及更高的电路性能。     

CMOS电压基准的设计原理

电压基准是集成电路一个重要的构成单元。结合多年设计经验，介绍了五类CMOS电压基准的设计原理、理论推导、参考电路、特点和主要性能指标，给出了主要参数的计算公式。最后，对各种CMOS电压基准的性能进行了比较。     

一种新型900MHz CMOS低噪声放大器的设计

对两种低噪声放大器(LNA)的构架进行了比较,详细推导了共源LNA的噪声系数与输入晶体管栅宽的关系及优化方法,设计了一种采用0.6 μ m标准CMOS工艺,工作于900MHz的新型差分低噪声放大器.在900MHz时,噪声系数为1.5 dB的情况下可提供22.5 dB的功率增益,-3dB带宽为1 50MHz,S11达到-38dB,消耗的电流为5mA.     

2.1 GHz射频CMOS混频器设计

设计了一个用于第三代移动通信的2.1 GHz CMOS下变频混频器,采用TsMC 0.25 μm CMOS工艺.在设计中,用LC振荡回路作电流源实现低电压;并用增大电流和降低跨导的方法提高线性度.在Cadence RF仿真器中对电路进行了模拟,在1.8 V电源电压下,仿真结果为:1 dB压缩点PtdB-10.65 dBm,lIP3 1.25 dBm,转换增益7 dB,噪声系数10.8 dB,功耗14.4 mW,且输入输出端口实现了良好的阻抗匹配.并用Cadence中的Virtuoso Layout Editor软件绘制了电路的版图.     

CMOS Power-Efficient Buffers and Amplifiers

In this paper, some topologies of novel power-efficient single-ended and fully differential amplifiers and buffers are presented. The reduction of the power dissipation has been ensured through the application of an adaptive biasing architecture which gives a current dependent on the input differential voltage. This allows the minimization of the stand-by power consumption without affecting the transient characteristics. The proposed topology, implemented in a standard CMOS technology, has been applied in the design of input and output stages of low-power amplifiers and voltage buffers, considering them also in the fully differential version. Simulation and measurement results showing good general performance will be also presented.     

基于90nm CMOS工艺的一种10位低功耗SAR A/D转换器

Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.     

A 10-bit low power SAR A/D converter based on 90 nm CMOS

Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.