Characterization of current-voltage (I-V) and capacitance-voltage-frequency (C-V-f) features of Al/SiO2/p-Si (MIS) Schottky diodes

The current-voltage (I-V) characteristics of metal-insulator-semiconductor Al/SiO₂/p-Si (MIS) Schottky diodes were measured at room temperature (300 K). In addition, capacitance-voltage-frequency (C-V-f) characteristics are investigated by considering the interface states (N_ss) at frequency range 100 kHz to 1 MHz. The MIS Schottky diode having interfacial insulator layer thickness of 33 Å, calculated from the measurement of the insulator capacitance in the strong accumulation region. At each frequency, the measured capacitance decreases with increasing frequency due to a continuous distribution of the interface states. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_b) values of 1.766 and 0.786 eV, respectively, were obtained from a forward bias I-V plot. In addition, the interface states distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) for the Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer, the interface states and barrier inhomogeneity of the device. As expected, the C-V curves gave a barrier height value higher than those obtained from I-V measurements. This discrepancy is due to the different nature of the I-V and C-V measurement techniques.     

On the temperature dependence of series resistance and interface states in Al/SiO2/p-Si (MIS) Schottky diodes

The capacitance-voltage-temperature (C-V-T) and conductance-voltage-temperature (G/w-V-T) characteristics of metal-semiconductor (Al/p-Si) Schottky diodes with thermal growth interfacial layer were investigated by considering series resistance effect in the wide temperature range (80-400 K). It is found that in the presence of series resistance, the forward bias C-V plots exhibit a peak, and experimentally shows that the peak positions shift towards higher positive voltages with increasing temperature, and the peak value of the capacitance has a maximum at 80 K. The C-V and (G/w-V) characteristics confirm that the N_ss and R_s of the diode are important parameters that strongly influence the electric parameters in (Al/SiO₂/p-Si) MIS Schottky diodes. The crossing of the G/w-V curves appears as an abnormality when seen with respect to the conventional behaviour of the ideal MS or MIS Schottky diode. It is thought that the presence of a series resistance keeps this intersection hidden and unobservable in homogeneous Schottky diodes, but it appears in the case of inhomogeneous Schottky diode. In addition, the high frequency (C_m) and conductance (G_m/w) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance.     

The effects of surface states and series resistance on the performance of Au/SnO2/n-Si and Al/SnO2/p-Si (MIS) Schottky barrier diodes

We have fabricated two types of Schottky barrier(SBDs),Au/SnO₂/n-Si (MIS1) and Al/SnO₂/p-Si (MIS2), to investigate the surface (N_ss) and series resistance (R_s) effect on main electrical parameters such as zero-bias barrier height (Φ_Bo) and ideality factor (n) for these SBDs. The forward and reverse bias current–voltage (I–V) characteristics of them were measured at 200 and 295 K, and experimental results were compared with each other. At temperatures of 200 and 295 K, Φ_Bo, n, N_ss and R_s for MIS1 Schottky diodes (SDs) ranged from 0.393 to 0.585 eV, 5.70 to 4.75, 5.42×10¹³ to 4.27×10¹³ eV^?1 cm^?2 and 514 to 388 Ω, respectively, whereas for MIS2 they ranged from 0.377 to 0.556 eV, 3.58 to 2.1, 1.25×10¹⁴ to 3.30×10¹⁴ eV^?1 cm^?2 and 312 to 290 Ω, respectively. The values of n for two types of SBDs are rather than unity and this behavior has been attributed to the particular distribution of N_ss and interfacial insulator layer at the metal/semiconductor interface. In addition, the temperature dependence energy density distribution profiles of N_ss for both MIS1 and MIS2 SBDs were obtained from the forward bias I–V characteristics by taking into account the bias dependence of effective barrier height (Φ_e) and R_s. Experimental results show that both N_ss and R_s values should be taken into account in the forward bias I–V characteristics. It has been concluded that the p-type SBD (MIS2) shows a lower barrier height (BH), lower R_s, n and N_ss compared to n-type SBD (MIS1), which results in higher current at both 200 and 295 K.     

Calculation from the current-voltage and capacitance-voltage measurements of characteristics parameters of Cd/CdS/n-Si/Au-Sb structure with CdS interface layer grown on n-Si substrate by SILAR method

The CdS thin film has been directly formed on n-type Si substrate to form an interfacial layer between cadmium (Cd) and n-type Si with Successive Ionic Layer Adsorption and Reaction (SILAR) method. An Au-Sb electrode has been used as an ohmic contact. The Cd/CdS/n-Si/Au-Sb structure has demonstrated clearly rectifying behaviour by the current-voltage (I-V) curves studied at room temperature. The characteristics parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au-Sb structure have been calculated from the forward bias I-V and reverse bias C⁻²-V characteristics. The diode ideality factor and the barrier height have been calculated as n = 2.06 and Φ_b = 0.92 eV by applying a thermionic emission theory, respectively. The diode shows non-ideal I-V behaviour with an ideality factor greater than unity that can be ascribed to the interfacial layer, the interface states and the series resistance. At high current densities in the forward direction, the series resistance (R_s) effect has been observed. The values of R_s obtained from dV/d(lnI)-I and H(I)-I plots are near to each others (R_s = 182.24 Ω and R_s = 186.04 Ω, respectively). This case shows the consistency of the Cheung′s approach. In the same way, the barrier height calculated from C⁻² -V characteristics varied from 0.698 to 0.743 eV. Furthermore, the density distribution of interface states (N_ss) of the device has been obtained from the forward bias I-V characteristics. It has been seen that, the N_ss has almost an exponential rise with bias from the mid gap toward the bottom of conduction band.     

On the profile of temperature dependent series resistance in Al/Si3N4/p-Si (MIS) Schottky diodes

The temperature dependence of capacitance-voltage (C-V) and conductance-voltage (G/w-V) characteristics of metal-insulator-semiconductor (Al/Si₃N₄/p-Si) Schottky barrier diodes (SBDs) was investigated by considering series resistance effect in the temperature range of 80-300 K. It is found that in the presence of series resistance, the forward bias C-V plots exhibit a peak, and experimentally show that the peak positions with a maximum at 260 K shift toward lower voltages with increasing temperature. The C-V and (G/w-V) characteristics confirm that the interface state density (N_ss) and series resistance (R_s) of the diode are important parameters that strongly influence the electric parameters of MIS structures. The crossing of the G/w-V curves appears as an abnormality compared to the conventional behavior of ideal Schottky diode. It is thought that the presence of series resistance keeps this intersection hidden and unobservable in homogeneous Schottky diodes, but it appears in the case of inhomogeneous Schottky diode. In addition, the high frequency (C_m) and conductance (G_m/w) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance.     

Electrical characterization of MS and MIS structures on AlGaN/AlN/GaN heterostructures

The forward and reverse bias I-V, C-V, and G/ω-V characteristics of (Ni/Au) Schottky barrier diodes (SBDs) on the Al_0.22Ga_0.78N/AlN/GaN high-electron-mobility-transistor (HEMTs) without and with SiN_x insulator layer were measured at room temperature in order to investigate the effects of the insulator layer (SiN_x) on the main electrical parameters such as the ideality factor (n), zero-bias barrier height (Ф_B0), series resistance (R_s), interface-state density (N_ss). The energy density distribution profiles of the N_ss were obtained from the forward bias I-V characteristics by taking into account the voltage dependence of the effective barrier height (Ф_e) and ideality factor (n_V) of devices. In addition, the N_ss as a function of E_c-E_ss was determined from the low-high frequency capacitance methods. It was found that the values of N_ss and R_s in SBD HEMTs decreases with increasing insulator layer thickness.     

The effect of Mo-doped PVC+TCNQ interfacial layer on the electrical properties of Au/PVC+TCNQ/p-Si structures at room temperature

The effect of Mo-doped and undoped PVC+TCNQ interfacial layer on electrical characteristics of a Au/PVC+TCNQ/p-Si structure was investigated using current–voltage (I–V), capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements at room temperature. The energy dependent interface states density (N_ss) was obtained from the forward bias I–V data by taking into account voltage dependent effective barrier height (Φ_e) for two diodes, i.e. with and without Mo doping. The voltage dependent resistance (R_i) of structures was also obtained using Ohm׳s law and the method of Nicollian and Brews for the diodes. In order to eliminate the effect of series resistance (R_s), C and G/ω at high frequency values were corrected. N_ss and R_s values were compared between the diodes and experimental results showed that N_ss and R_s values of the Mo-doped PVC+TCNQ structure are considerably lower than those of the undoped PVC+TCNQ structure. The other important parameters such as ideality factor (n), reverse saturation current (I_s), zero-bias barrier heights (Φ_Bo) and R_s were obtained from forward bias I–V data by using I–V, Cheung and Norde methods. Experimental results confirmed that the Mo-doped (PVC+TCNQ) layer considerably improved the performance of the Au/PVC+TCNQ/p-Si structure.     

Effects of PCBM concentration on the electrical properties of the Au/P3HT:PCBM/n-Si (MPS) Schottky barrier diodes

In this study, the gold/poly(3-hexylthiophene):[6,6]-phenyl C61 butyric acid methyl ester/n-type silicon (Au/P3HT:PCBM/n-Si) metal–polymer–semiconductor (MPS) Schottky barrier diodes (SBDs) were investigated in terms of the effects of PCBM concentration on the electrical parameters. The forward and reverse bias current–voltage (I–V) characteristics of the Au/P3HT:PCBM/n-Si MPS SBDs fabricated by using the different P3HT:PCBM mass ratios were studied in the dark, at room temperature. The main electrical parameters, such as ideality factor (n), barrier height (Φ_B0), series resistance (R_s), shunt resistance (R_sh), and density of interface states (N_ss) were determined from I–V characteristics for the different P3HT:PCBM mass ratios (2:1, 6:1 and 10:1) used diodes. The values of n, R_s, Φ_B0, and N_ss were reduced, while the carrier mobility and current were increased, by increasing the PCBM concentration in the P3HT:PCBM organic blend layer. The ideal values of electrical parameters were obtained for 2:1 P3HT:PCBM mass ratio used diode. This shows that the electrical properties of MPS diodes strongly depend on the PCBM concentration of the P3HT:PCBM organic layer. Moreover, increasing the PCBM concentration in P3HT:PCBM organic blend layer improves the quality of the Au/P3HT:PCBM/n-Si (MPS) SBDs which enables the fabrication of high-quality electronic and optoelectronic devices.     

Series resistance calculation for Ag contacts on single crystal layered p-SnS and p-SnSe compound semiconductors in the wide temperature range

This paper summarizes the first results of characteristics parameters obtained from current-voltage (I-V) measurements for Ag/p-SnS and Ag/p-SnSe structure. The reverse and forward bias current-voltage characteristics of Ag Schottky contacts on a Bridgman-Stockbarger grown p-SnS and p-SnSe layered semiconducting material have been measured at various temperatures. We have tried to determine contact properties such as apparent barrier heights Φ_B0, ideality factor n and series resistance R_s. The apparent barrier height and ideality factor calculated by using thermionic emission theory were found to be strongly temperature dependent. Evaluating forward I-V data reveals a decrease at the apparent barrier height, but an increase at the ideality factor with decrease in temperature. It is shown that the values of R_s estimated from Cheung’s method were strongly temperature dependent and decreased with increasing temperature. It has been found that both contacts are of Schottky type.     

The C-V-f and G/ω-V-f characteristics of Al/SiO2/p-Si (MIS) structures

The frequency dependence of capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) structures has been investigated taking into account the effect of the series resistance (R_s) and interface states (N_ss) at room temperature. The C-V and G/ω-V measurements have been carried out in the frequency range of 1 kHz to 1 MHz. The frequency dispersion in capacitance and conductance can be interpreted only in terms of interface states and series resistance. The N_ss can follow the ac signal and yield an excess capacitance especially at low frequencies. In low frequencies, the values of measured C and G/ω decrease in depletion and accumulation regions with increasing frequencies due to a continuous density distribution of interface states. The C-V plots exhibit anomalous peaks due to the N_ss and R_s effect. It has been experimentally determined that the peak positions in the C-V plot shift towards lower voltages and the peak value of the capacitance decreases with increasing frequency. The effect of series resistance on the capacitance is found appreciable at higher frequencies due to the interface state capacitance decreasing with increasing frequency. In addition, the high-frequency capacitance (C_m) and conductance (G_m/ω) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance. Experimental results show that the locations of N_ss and R_s have a significant effect on electrical characteristics of MIS structures.     

On the energy distribution of interface states and their relaxation time and capture cross section profiles in Al/SiO2/p-Si (MIS) Schottky diodes

The energy distribution profile of the interface states (N_ss) and their relaxation time (τ) and capture cross section (σ_p) of metal-insulator-semiconductor (Al/SiO₂/p-Si) Schottky diodes have been investigated by using the high-low frequency capacitance and conductance methods. The capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of these devices were investigated by considering series resistance (R_s) effects in a wide frequency range (5 kHz-1 MHz.). It is shown that the capacitance of the Al/SiO₂/p-Si Schottky diode decreases with increasing frequency. The increase in capacitance especially at low frequencies results form the presence of interface states at Si/SiO₂ interface. The energy distributions of the interface states and their relaxation time have been determined in the energy range of (0.362-E_v)-(0.512-E_v) eV by taking into account the surface potential as a function of applied bias obtained from the measurable C-V curve (500 Hz) at the lowest frequency. The values of the interface state density (N_ss) ranges from 2.34 × 10¹² to 2.91 ×  10¹² eV⁻¹/cm², and the relaxation time (τ) ranges from 1.05 × 10⁻⁶ to 1.58 × 10⁻⁴ s, showing an exponential rise with bias from the top of the valance band towards the mid-gap.     

The frequency and voltage dependent electrical characteristics of Al-TiW-Pd2Si/n-Si structure using I-V, C-V and G/ω-V measurements

The forward and reverse bias capacitance-voltage (C-V) and conductance-voltage (G/w-V) characteristics of Al-TiW-Pd₂Si/n-Si structures have been investigated over a wide frequency range of 5 kHz-5 MHz. These measurements allow to us the determination of the interface states density (N_ss) and series resistance (R_s) distribution profile. The effect of R_s on C and G is found noticeable at high frequencies. The C-V-f and G/w-V-f characteristics of studied structures show fairly large frequency dispersion especially at low frequencies due to N_ss in equilibrium with the semiconductor. The N_ss profile was obtained both forward bias current-voltage (I-V) characteristics by using into account the bias dependent of the ideality factor and effective barrier height (Φ_e) and low frequency (C_LF)-high frequency (C_HF) method. The plot of series resistance vs. voltage for the low frequencies gives a peak, decreasing with increasing frequencies. The frequency dependent C-V and G/w-V characteristics confirm that the R_s and N_ss of the Al-TiW-Pd₂Si/n-Si structures are important parameters that strongly influence the electric parameters in device.     

Characterization of interface states at Ni/nCdF2 Schottky barrier type diodes and the effect of CdF2 surface preparation

Two Schottky diodes were fabricated by evaporation of nickel on to an n-type CdF₂:YF₃ semiconductor. Diode A was prepared on a slightly etched polished surface and diode B on an unpolished strongly etched surface. The current-voltage (I-V), capacitance-voltage (C-V), and conductance-voltage (G-V) characteristics were determined at room temperature. Both diodes showed non-ideal I-V behaviour with ideality factors 1.5 and 2.0, respectively and are thought to have a metal-interface layer-semiconductor configuration. Under forward bias, the admittance showed large frequency dispersion possibly caused by the interface states in thermal equilibrium with the semiconductor. Analysis of the C-V data in terms of Lehovec's model of an interface state continuum required the supposition of two time constants differing by 2 to 3 orders of magnitude. The characteristic parameters of the interface states (energy position, density, time constant and capture cross-section) were obtained for the values of the forward bias in the range 0.0 V ≦ V ≦ 0.2 V. The diode B is found to have the interface state densities about two orders of magnitude higher than the diode A which may be attributed to the different surface treatments. The C-V measurements at 100 kHz also indicated the presence of a deep donor trap about 0.6 eV below the conduction band edge in diode A.     

Ta/Si Schottky diodes fabricated by magnetron sputtering technique

Electrical properties of Ta/n-Si and Ta/p-Si Schottky barrier diodes obtained by sputtering of tantalum (Ta) metal on semiconductors have been investigated. The characteristic parameters of these contacts like barrier height, ideality factor and series resistance have been calculated using current voltage (I-V) measurements. It has seen that the diodes have ideality factors more than unity and the sum of their barrier heights is 1.21 eV which is higher than the band gap of the silicon (1.12 eV). The results have been attributed the effects of inhomogeneities at the interface of the devices and native oxide layer. In addition, the barrier height values determined using capacitance-voltage (C-V) measurements have been compared the ones obtained from I-V measurements. It has seen that the interface states have strong effects on electrical properties of the diodes such as C-V and R_s-V measurements.     

The role of the interface insulator layer and interface states on the current-transport mechanism of Schottky diodes in wide temperature range

In order to interpret in detail the experimentally observed current-voltage-temperature (I-V-T) and capacitance-voltage-temperature (C-V-T) results of Al/p-Si metal-semiconductor Schottky barrier diodes (SBDs) we have been examined the samples in the temperature range of 150-375 K. In the calculation method, to confirm the relationship between the I-V-T and C-V-T results, we have reported a modification which includes the ideality factor, n, and tunnelling parameter δχ^1/2 in the forward bias current characteristics. In the intermediate bias voltage region (0.1 < V < 0.6 V), the semi-logarithmic plots of the forward I-V-T curves were found to be linear. From the reverse saturation currents I₀ obtained by extrapolating the linear region of curves to zero applied voltage, the values of zero bias barrier heights ?_B0 were calculated at each temperature. The values of ideality factor calculated from the slope of each curves were plotted as a function of temperature. The values of n are 3.41-1.40 indicating that the Al/p-Si diode does obey the thermionic field emission (TFE) mechanism rather than the other transport mechanism, particularly at low temperature. The high value of ideality factors is attributed to high density of interface states in the SBDs. The temperature dependence energy density distribution profile of interface state was obtained from the forward bias I-V-T measurements by taking into account the bias dependence of the effective barrier height and ideality factor. The interface states density N_ss decreasing with increasing temperature was interpreted by the result of atomic restructuring and reordering at the metal-semiconductor interface. After the modification was made to the forward current expression, we obtained a good agreement between the values of barrier height obtained from both methods over a wide temperature.     

The interface states analysis of the MIS structure as a function of frequency

The energy distribution of interface states (N_ss) and their relaxation time (τ) were of the fabricated the Al/SiO₂/p-Si (MIS) structures were calculated using the forward bias current-voltage (I-V), capacitance-frequency (C-f) and conductance-frequency (G-f) measurements. Typical ln[I/(1 − exp(−qV/kT)] versus V characteristics of MIS structure under forward bias show one linear region. From this region, the slope and the intercept of this plot on the current axis allow to determine the ideality factor (n), the barrier height (Φ_b) and the saturation current (I_S) evaluated to 1.32, 0.77 eV and 3.05 × 10⁻⁹ A, respectively. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer at metal-semiconductor interface, the interface states and barrier inhomogeneity of the device. The energy distribution of interface states (N_ss) and their relaxation time (τ) have been determined in the energy range from (0.37 − E_v) to (0.57 − E_v) eV. It has been seen that the N_ss has almost an exponential rise with bias from the mid gap toward the top of valance band. In contrary to the N_ss, the relaxation time (τ) shows a slow exponential rise with bias from the top of the E_v towards the mid gap energy of semiconductor. The values of N_ss and τ change from 6.91 × 10¹³ to 9.92 × 10¹³ eV⁻¹ cm⁻² and 6.31 × 10⁻⁴ to 0.63 × 10⁻⁴ s, respectively.     

On the profile of frequency and voltage dependent interface states and series resistance in (Ni/Au)/Al0.22Ga0.78N/AlN/GaN heterostructures by using current-voltage (I-V) and admittance spectroscopy methods

In order to explain the experimental effect of interface states (N_ss) and series resistance (R_s) of device on the non-ideal electrical characteristics, current-voltage (I-V), capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of (Ni/Au)/Al_0.22Ga_0.78N/AlN/GaN heterostructures were investigated at room temperature. Admittance measurements (C-V and G/ω-V) were carried out in frequency and bias voltage ranges of 2 kHz-2 MHz and (−5 V)-(+5 V), respectively. The voltage dependent R_s profile was determined from the I-V data. The increasing capacitance behavior with the decreasing frequency at low frequencies is a proof of the presence of interface states at metal/semiconductor (M/S) interface. At various bias voltages, the ac electrical conductivity (σ_ac) is independent from frequencies up to 100 kHz, and above this frequency value it increases with the increasing frequency for each bias voltage. In addition, the high-frequency capacitance (C_m) and conductance (G_m/ω) values measured under forward and reverse bias were corrected to minimize the effects of series resistance. The results indicate that the interfacial polarization can more easily occur at low frequencies. The distribution of N_ss and R_s is confirmed to have significant effect on non-ideal I-V, C-V and G/ω-V characteristics of (Ni/Au)/Al_0.22Ga_0.78N/AlN/GaN heterostructures.     

A compare of electrical characteristics in Al/p-Si (MS) and Al/C20H12/p-Si (MPS) type diodes using current–voltage (I–V) and capacitance–voltage (C–V) measurements

In this study, both the metal-semiconductor (MS) and metal-polymer-semiconductor (MPS), (Al/C₂₀H₁₂/p-Si), type Schottky barrier diodes (SBDs) were fabricated using spin coating method and they were called as D₁ and D₂ diodes, respectively. Their electrical characterization have been investigated and compared using the forward and reverse bias I–V and C–V measurements at room temperature. The main electrical parameters such as ideality factor (n), reverse saturation current (I_o), zero-bias barrier height (Φ_Bo), series (R_s) and shunt (R_sh) resistances, energy dependent profile of interface states (N_ss), the doping concentration of acceptor atoms (N_A) and depletion layer width (W_D) were determined and compared each other and literature. The rectifying ratio (RR) and leakage current (I_R) at ±3 V were found as 2.06×10³, 1.61×10⁻⁶ A and 15.7×10³, 2.75×10⁻⁷ A for D₁ and D₂, respectively. Similarly, the R_s and R_sh values of these diodes were found as 544 Ω, 10.7 MΩ and 716 Ω and 1.83 MΩ using Ohm’s Law, respectively. In addition, energy and voltage dependent profiles of N_ss were obtained using the forward bias I–V data by taking into account voltage dependent effective barrier height (Φ_e) and n and low-high frequency capacitance (C_LF–C_HF) methods, respectively. The obtained value of N_ss for D₂ (MPS) diode at about the mid-gap of Si is about two times lower than D₁ (MS) type diode. Experimental results confirmed that the performance in MPS type SBD is considerably high according to MS diode in the respect of lower values of N_ss, R_s and I_o and higher values of RR and R_sh.     

Electrical characteristics and inhomogeneous barrier analysis of Au-Be/p-InSe:Cd Schottky barrier diodes

We have identically prepared Au-Be/p-InSe:Cd Schottky barrier diodes (SBDs) (21 dots) on the InSe:Cd substrate. The electrical analysis of Au-Be/p-InSe:Cd structure has been investigated by means of current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) measurements at 296 K temperature in dark conditions. The effective barrier heights and ideality factors of identically fabricated Au-Be/p-InSe:Cd SBDs have been calculated from their experimental forward bias current-voltage (I-V) characteristics by applying a thermionic emission theory. The BH values obtained from the I-V characteristics have varied between 0.74 eV and 0.82 eV with values of ideality factors ranging between 1.49 and 1.11 for the Au-Be/p-InSe:Cd SBDs. It has been determined a lateral homogeneous barrier height value of approximately 0.82 eV for these structures from the experimental linear relationship between barrier heights and ideality factors. The Schottky barrier height (SBH) value has been obtained from the reverse-bias C-V characteristics of Au-Be/p-InSe:Cd SBD for only one diode. At high currents in the forward direction, the series resistance effect has been observed. The value of series resistance has been determined from I-V measurements using Cheung’s and Norde’s methods.     

Electrical and interfacial properties of Au/P3HT:PCBM/n-Si Schottky barrier diodes at room temperature

In this study, a gold/poly(3-hexylthiophene):[6,6]-phenyl C61 butyric acid methyl ester/n-type silicon (Au/P3HT:PCBM/n-Si) metal-polymer-semiconductor (MPS) Schottky barrier diode (SBD) was fabricated. To accomplish this, a spin-coating system and a thermal evaporation were used for preparation of a P3HT/PCBM layer system and for deposition of metal contacts, respectively. The forward- and reverse-bias current–voltage (I–V) characteristics of the MPS SBD at room temperature were studied to investigate its main electrical parameters such as ideality factor (n), barrier height (Φ_B), series resistance (R_s), shunt resistance (R_sh), and density of interface states (N_ss). The I–V characteristics have nonlinear behavior due to the effect of R_s, resulting in an n value (3.09) larger than unity. Additionally, it was found that n, Φ_B, R_s, R_sh, and N_ss have strong correlation with the applied bias. All results suggest that the P3HT/PCBM interfacial organic layer affects the Au/P3HT:PCBM/n-Si MPS SBD, and that R_s and N_ss are the main electrical parameters that affect the Au/P3HT:PCBM/n-Si MPS SBD. Furthermore, a lower N_ss compared with that of other types of MPS SBDs in the literature was achieved by using the P3HT/PCBM layer. This lowering shows that high-quality electronic and optoelectronic devices may be fabricated by using the Au/P3HT:PCBM/n-Si MPS SBD.