Investigation of Ta2O5/SiO2/4H-SiC MIS capacitors

Tantalum pentoxide (Ta₂O₅) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta₂O₅ of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta₂O₅. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta₂O₅ and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta₂O₅ at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta₂O₅/SiO₂/4H-SiC capacitors.     

Influence of the metal electrode on the characteristics of thermal Ta2O5 capacitors

The effect of various electrodes (Al, W, TiN) deposited by evaporation (Al) and sputtering (W, TiN) on the electrical characteristics of thermal thin film (15-35 nm) Ta₂O₅ capacitors has been investigated. The absolute level of leakage currents, breakdown fields, mechanism of conductivity, dielectric constant values are discussed in the terms of possible reactions between Ta₂O₅ and electrode material as well as electrode deposition process-induced defects acting as electrically active centers. The dielectric constant values are in the range 12-26 in dependence on both Ta₂O₅ thickness and gate material. The results show that during deposition of TiN and Al a reaction that worsens the properties of Ta₂O₅ occurs while there is not an indication for detectable reduction of Ta₂O₅ when top electrode is W, and the leakage current is 5-7 orders of magnitude lower as compared to Al and TiN-electroded capacitors. The high level of leakage current for TiN and Al gate capacitors are related to the radiation defects generated in Ta₂O₅ during sputtering of TiN, and damaged interface at the electrode due to a reaction between Al and Ta₂O₅, respectively. It is demonstrated that the quality of the top electrode affects the electrical characteristics of the capacitors and the sputtered W is found to be the best. The sputtered W gate provides Ta₂O₅ capacitors with a good quality: the current density <7 × 10⁻¹⁰ A/cm² at 1 V (0.7 MV/cm, 15 nm thick Ta₂O₅). W deposition is not accompanied by an introduction of a detectable damage leading to a change of the properties of the initial as-grown Ta₂O₅ as in the case of TiN electrode. Damage introduced during TiN sputtering is responsible for current deterioration (high leakage current) and poor breakdown characteristics. It is concluded that the sputtered W top electrode is a good candidate as a top electrode of storage capacitors in dynamic random access memories giving a stable contact with Ta₂O₅, but sputtering technique is less suitable (favorable) for deposition of TiN as a metal electrode due to the introduction of radiation defects causing both deterioration of leakage current and poor breakdown characteristics.     

Effects of annealing conditions on the properties of tantalum oxide films on silicon substrates

The formation of a SiO₂ layer at the Ta₂O₅/Si interface is observed by annealing in dry O₂ or N₂ and the thickness of this layer increases with an increase in annealing temperature. Leakage current of thin (less than 40 nm thick) Ta₂O₅ films decreases as the annealing temperature increases when annealed in dry O₂ or N₂. The dielectric constant vs annealing temperature curve shows a maximum peak at 750 or 800° C resulting from the crystallization of Ta₂O₅. The effect is larger in thicker Ta₂O₅ films. But the dielectric constant decreases when annealed at higher temperature due to the formation and growth of a SiO₂ layer at the interface. The flat band voltage and gate voltage instability as a function of annealing temperature can be explained in terms of the growth of interfacial SiO₂. The electrical properties of Ta₂O₅ as a function of annealing conditions do not depend on the fabrication method of Ta₂O₅ but strongly depend on the thickness of Ta₂O₅ layer.     

The properties of high-k gate dielectric films deposited on HRSOI

In this paper, HfO₂ dielectric films with blocking layers (BL) of Al₂O₃ were deposited on high resistivity silicon-on-insulator (HRSOI), and the interfacial and electrical properties are reported. High-resolution transmission electron microscopy (HRTEM) indicated that BL could thin the interfacial layer, keep the interface smooth, and retain HfO₂ amorphous after annealing. Energy dispersive X-ray spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) confirmed that BL weaken Si diffusion and suppressed the further growth of HfSiO. Electrical measurements indicated that there was no hysteresis was observed in capacitance–voltage curves, and Flatband shift and interface state density is 0.05 V and −1.3 × 10¹² cm⁻², respectively.     

基于MIS电容器的Al2O3与In0.74Al0.26As的界面特性

采用In_0.74Al_0.26As/In_0.74Ga_0.26As/In_xAl_1-xAs异质结构多层半导体作为半导体层,制备了金属-绝缘体-半导体（MIS）电容器。其中,SiN_x和SiN_x/Al₂O₃分别作为MIS电容器的绝缘层。高分辨率透射电子显微镜和X射线光电子能谱的测试结果表明,与通过电感耦合等离子体化学气相沉积生长的SiN_x相比,通过原子层沉积生长的Al2_O3可以有效地抑制Al₂O₃和In_0.74Al_0.26As界面的In₂O₃的含量。根据MIS电容器的电容-电压测量结果,计算得到SiN_x/Al₂O₃/In...     

Metal-silicon reaction rates—the effects of capping

Evidence is presented showing that the presence of the commonly used anti-reflection coating material Ta₂O₅ on the free surface of contact metallization can either suppress or enhance, depending on the system, the interaction that takes place at elevated temperatures between the metallization and the underlying Si. The cap layer is shown to suppress both the generation and annihilation of vacancies at the free surface of the metal which are necessary to support metal-Si interactions. Evidence is also presented indicating that the mechanical condition of the free metal surface has a significant effect on the metal-silicon reaction rate.     

Effect of thermal oxide on the crystallization of the anodic Ta2O5 film

SEM and TEM investigations of the crystallization process have been performed on amorphous Ta₂O₅ films grown by electrochemical oxidation of Ta foils. It was found that kinetics of crystallization and final structure of the anodic Ta₂O₅ film depend strongly on the thickness of the thermal oxide layer on the surface of the original Ta substrate. Two different modes of crystallization were detected for the substrate with native surface oxide and with the thermal oxide grown at elevated temperatures. Aborting of the crystallization was shown to be possible using short heating of the Ta₂O₅/Ta san dwiches which cuts crystalline inclusions grown into the amorphous matrix of the anodic Ta₂O₅ film from the Ta surface.     

Influence of oxidation temperature on the microstructure and electrical properties of Ta2O5 on Si

The effect of the oxidation temperature (673-873 K) on the microstructural and electrical properties of thermal Ta₂O₅ thin films on Si has been studied. Auger electron spectroscopy and X-ray photoelectron spectroscopy results revealed that the films are non-stoichiometric in the depth; an interfacial transition layer between tantalum oxide and Si substrate, containing presumably SiO₂ was detected. It has been found by X-ray diffraction that the amorphous state of Ta₂O₅ depends on both the oxidation temperature and the thickness of the films—the combination of high oxidation temperature (>823 K) and thickness smaller than 50 nm is critical for the appearance of a crystal phase. The Ta₂O₅ layers crystallize to the monoclinic phase and the temperature of the phase transition is between 773 and 823 K for the thinner layers (<50 nm) and very close to 873 K for the thicker ones. The electrical characterization (current/voltage; capacitance/voltage) reveals that the optimal oxidation temperature for achieving the highest dielectric constant (∼32) and the lowest leakage current (10⁻⁸ A/cm² at 1 MV/cm applied field) is 873 K. The results imply that the poor oxidation related defects are rather the dominant factor in the leakage current than the crystallization effects.     

用于GaAs射频集成电路的不同厚度氧化铝MIM 电容的研究

本文研究了不同厚度的氧化铝对MIM电容直流和射频特性的影响。在1MHz下,对于20nm氧化铝MIM电容,其拥有3850 pF/mm₂的高电容密度和可接受的681 ppm/V₂的VCC-α电压系数。1MHz时突出的74 ppm/V₂VCC-α电压系数,8.2GHz谐振频率以及2GHz时41的Q值可以从100nm氧化铝MIM电容获得。采用GaAs工艺以及原子层淀积制造的高性能ALD氧化铝MIM电容很有可能成为GaAs射频集成电路很有前景的候选器件。     

Investigation of strontium tantalate thin films for high-k gate dielectric applications

Strontium tantalate (STO) films were grown by liquid-delivery (LD) metalorganic chemical vapor deposition (MOCVD) using Sr[Ta(OEt)₅(OC₂H₄OMe)]₂ as precursor. The deposition of the films was investigated in dependence on process conditions, such as substrate temperature, pressure, and concentration of the precursor. The growth rate varied from 4 to 300 nm/h and the highest rates were observed at the higher process temperature, pressure, and concentration of the precursor. The films were annealed at temperatures ranging from 600 to 1000 °C. Transmission electron microscopy (TEM), X-ray diffraction (XRD), and ellipsometry indicated that the as-deposited and the annealed films were uniform and amorphous and a thin (>2 nm) SiO₂ interlayer was found. Crystallization took place at temperatures of about 1000 °C. Annealing at moderate temperatures was found to improve the electrical characteristics despite different film thickness (effective dielectric constant up to 40, the leakage current up to 6×10⁻⁸ A/cm², and lowest midgap density value of 8×10¹⁰ eV⁻¹ cm⁻²) and did not change the uniformity of the STO films, while annealing at higher temperatures (1000 °C) created voids in the film and enhanced the SiO₂ interlayer thickness, which made the electrical properties worse. Thus, annealing temperatures of about 800 °C resulted in an optimum of the electrical properties of the STO films for gate dielectric applications.     

Analysis of interface trap density of metal-oxide-semiconductor devices with Pr2O3 gate dielectric using conductance method

In this study, the interface trap density of metal-oxide-semiconductor (MOS) devices with Pr₂O₃ gate dielectric deposited on Si is determined by using a conductance method. In order to determine the exact value of the interface trap density, the series resistance is estimated directly from the impedance spectra of the MOS devices. Subsequently, the dispersion characteristics are numerically analyzed on the basis of a statistical model. Lastly, the process-dependent interface trap density of Pr₂O₃ is evaluated. It is concluded that high-pressure annealing and a superior quality interfacial SiO₂ layer are of crucial importance for achieving a sufficiently low interface trap density.     

Hf-doped Ta2O5 stacks under constant voltage stress

The stress-induced leakage current in Hf-doped Ta₂O₅ layers (7; 10 nm) under constant voltage stress at gate injection was investigated in order to assess the mechanisms of conduction, the traps involved and the effect of Hf doping. The amount of Hf is found to affect the conduction mechanisms, the temperature dependence of the leakage current and the current response to the stress. A significant leakage current increase is observed only when the stress voltage and/or stress time exceed the corresponding threshold values, where the charge trapping at the pre-existing traps dominates below and defect generation above these threshold values. The energy levels of the traps responsible for the current transport are estimated. The stress effect on dominant conduction mechanisms appears quite weak, and the nature of the traps controlling the current transport before and after the stress seems to be nearly identical. The results indicate that the constant voltage stress affects the pre-existing traps in Hf-doped Ta₂O₅ and modifies their parameters, but there is no evidence for stress-induced generation of traps with completely new nature different from oxygen-vacancy related defects.     

Influence of post deposition annealing on Y2O3-gated GaAs MOS capacitors and their reliability issues

The feasibility of employing yttrium oxide (Y₂O₃) as high-k gate dielectrics for GaAs metal-oxide-semiconductor (MOS) devices has been investigated. MOS capacitors were fabricated using RF-sputtered deposited Y₂O₃ films on NH₄OH treated n-GaAs substrate. Indeed high-k (Y₂O₃)/GaAs MOS capacitors exhibiting fairly good electrical characteristics, for instance, especially low leakage current density, low hysteresis and allowable density of interface states, have been achieved. The effects of several annealing treatments on Y₂O₃-gated GaAs MOS capacitors have been investigated in order to optimize the process conditions. A decrease in accumulation capacitance (C_acc) following PDA effectively increases the equivalent oxide thickness (EOT), which is predicted to be correlated with the growth and continuous increase in the physical thickness of a lower-k inter-layer sandwiched between Y₂O₃ and GaAs. However, leakage currents and interface trap densities are reduced with higher values of annealing temperature. The variation of current density with an equivalent oxide thickness (EOT) has also been investigated.     

Losses in tantalum pentoxide waveguides

Thin films of tantalum pentoxide for possible use as waveguides have been prepared by reactive sputtering and by thermal and anodic oxidation of sputtered tantalum films. Measurements have been made of the losses in these films for different guided modes. These results have been analyzed to determine the loss mechanism. The losses do not fit the Rayleigh scattering theory precisely and the deviation is attributed to absorption by impurities at the surface as well as in the bulk. The effects of bulk and surface loss mechanisms have been obtained and causes of these are discussed.     

Properties of solid-state electrochromic cells using Ta2O5 as electrolyte

Solid-state electrochromic (EC) cells (ITO/WO₃/Ta₂O₅/ITO), where ITO is indium-tin-oxide, were fabricated. Individual films were prepared by rf sputtering. The conduction mechanism in the Ta₂O₅ electrolyte was considered from the measurement of ac conductivity. Absorption spectra, coloration efficiency and memory characteristics of the EC cells were investigated. These results are compared with those of EC cells with liquid electrolytes.     

Excellent performance of gas sensor based on In2O3-Fe2O3 nanotubes

In₂O₃-Fe₂O₃ nanotubes are synthesized by an electrospinning method. The as-synthesized materials are characterized by scanning electron microscope and X-ray powder diffraction. The gas sensing results show that In₂O₃-Fe₂O₃ nanotubes exhibit excellent sensing properties to acetone and formaldehyde at different operating temperatures. The responses of gas sensors based on In₂O₃-Fe₂O₃ nanotubes to 100 ppm acetone and 100 ppm formaldehyde are 25 (240℃) and 15 (260℃), and the response/recovery times are 3/7 s and 4/7 s, respectively. The responses of In₂O₃-Fe₂O₃ nanotubes to 1 ppm acetone (240℃) and formaldehyde (260℃) are 3.5 and 1.8, respectively. Moreover, the gas sensor based on In₂O₃-Fe₂O₃ nanotubes also possesses an excellent selectivity to acetone and formaldehyde.     

Temperature treatment of nano-scaled barium titanate filler to improve the dielectric properties of high-k polymer based composites

A commercially available nano-scaled barium titanate powder was compounded with a polyester-styrene reactive resin to create a high-k polymer-composite material. The influence of a temperature treatment on the filler was examined for treatment temperatures between 500 and 1200 °C. As a result grain and particle growth as well as lattice relaxation was induced into the powder particles. The resulting composite permittivity rises from 9.2 to 25.0 (at room temperature, 1 kHz, filler load 60 wt%/∼22 vol%) and the dielectric loss factor drops to values below 0.005 as a result of this treatment. The changes in lattice structure, powder morphology and composite viscosity were determined by XRD, SEM, BET, He-pycnometry and rheology measurements. The temperature dependency of the dielectric properties of the pure polymer and the composite were measured between −60 and 70 °C. The temperature dependency of the polymer matrix is superimposed with the temperature characteristic of the BaTiO₃.     

CNTs/Fe3O4复合电泳提高CNTs阴极场发射性能

A simple CNT/Fe₃O₄ composite electrophoretic deposition method to improve the field emission cathode properties of carbon nanotubes (CNTs) is proposed. It is found that CNT/Fe₃O₄ composite electrophoretic deposition leads to better field emission performance than that of single CNT electrophoretic deposition. The result is investigated using SEM, J-E and FE. After the process, the turn-on electric field decreases from 0.882 to 0.500 V/μm at an emission current density of 0.1 mA/cm², and the latter increases from 0.003 to 1.137 mA/cm² at an electric field of 0.64 V/μm. CNT/Fe₃O₄ composite electrophoretic deposition is an easy and effective cathode preparation for field emission display applications.     

电子束辐照下的石墨烯上的原子层沉积Al2O3介质层

为了研究石墨烯与高k介质的结合,使用原子层沉积氧化铝在石墨衬底上。沉积前使用电子束辐照,观测到了氧化铝明显改善的形貌。归因于电子束辐照过程中的石墨层的无定形变化过程。     

Nanostructure effect of V2O5 buffer layer on performance of polymer-fullerene devices

Nanostructure of solar cell materials is often essential for the device performance. V₂O₅ nanobelt structure is synthesized with a solution process and further used as an anode buffer layer in polymer solar cells, resulting insignificantly improved power conversion efficiency (PCE of 2.71%) much higher than that of devices without the buffer layer (PCE of 0.14%) or with V₂O₅ powder as the buffer layer (1.08%). X-ray diffraction (XRD) results indicate that the V₂O₅ nanobelt structure has better phase separation while providing higher surface area for the P3HT:PCBM active layer to enhance photocurrent. The measured impedance spectrums show that the V₂O₅ nanobelt structure has faster charge transport than the powder material. This work clearly demonstrates that V₂O₅ nanobelt has great potential as a substitute of the conventionally used PEDOT-PSS buffer layer for high performance devices.