Very high-speed and high-accuracy current-steering CMOS D/A converter using a novel 3-D decoder

In this paper a 10-bit 1.2-GSample/s Nyquist current-steering CMOS digital-to-analog converter (DAC) is presented. Segmentation (90%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a novel 3-D thermometer decoding method which reduces the area, power consumption, and the number of control signals of the digital section. Simulation results show that the spurious-free-dynamic-range (SFDR) in Nyquist rate is better than 65 dB for sampling frequency up to 1.2-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates at only 2.4 V. Total power consumption in Nyquist rate measurement is 149 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.97 mm².     

A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC

In this paper a 12-bit current-steering hybrid DAC is implemented using AMS 0.35 μm CMOS process technology. The architecture and design methodology used for the implementation of the DAC offer advantages like design speed up, easiness in design and a small active area. The proposed hybrid DAC consists of four 3-bit parallel matched current-steering subDACs and resistive networks that properly weight the current output of each subDAC to obtain the overall voltage-mode output of the 12-bit hybrid DAC. The performance of the hybrid DAC is validated through static and dynamic performance metrics. Simulations indicate that the DAC has an accuracy of 12-bit and a SFDR higher than 66 dB in whole Nyquist frequency band. The simulated INL is better than 1 LSB, while simulated DNL is better than 0.25 LSB. At an update rate of 250 MS/s the SFDR for signals up to 10 MHz is higher than 66 dB. The Figure of Merit (FoM) of the implemented hybrid DAC is better than recently presented DACs with 12-bit resolutions and implemented using various process technologies. The proposed hybrid DAC supporting high update rates with good dynamic performance can be used as an alternative in various applications in industry including video, digital TV, cable modems etc.     

A 10-bit 250-MS/s binary-weighted current-steering DAC

This paper studies the impact of segmentation on current-steering digital-to-analog converters (DACs). Segmentation may be used to improve the dynamic behavior of the converter but comes at a cost. A method for reducing the segmentation degree is given. The presented chip, a 10-bit binary-weighted current-steering DAC, has >60 dB SFDR at 250 MS/s from DC to Nyquist. At 62.5 MHz signal frequency and 250 MS/s, we operated the device in 9-bit unary, 1-bit binary-weighted mode. The obtained 60 dB SFDR in this measurement demonstrates that the binary nature of the converter did not limit the SFDR. The chip draws 4 mW from a dual 1.5 V/1.8 V supply plus load currents. The active area is less than 0.35 mm/sup 2/ in a standard 1P-5M 0.18-/spl mu/m 1.8-V CMOS process. Both INL and DNL are below 0.1 LSB.     

12bit高稳定性数模转换器设计

设计了一款12 bit高稳定性控制类数模转换器(DAC),该DAC集成了带有稳定启动电路的新型低失调带隙基准源(BGR),改善了基准电路的稳定性以及对温度和工艺的敏感性;DAC采用了改进的两级电阻串结构,通过开关电阻匹配和特殊版图布局,在既不增加电路功耗又不扩大版图面积的前提下,提高了DAC的精度并降低了工艺浓度梯度对整体性能的影响.基于CSMC 0.5 μm 5 V 1P4M工艺对所设计的DAC芯片进行了流片验证.测试结果表明:常温下DAC的微分非线性(DNL)小于0.45 LSB,积分非线性(INL)小于1.5 LSB,并且在-55～125℃内DNL小于1 LSB,INL小于2.5 LSB;5V电源电压供电时功耗仅为3.5 mW,实现了高精度、高稳定性的设计目标.     

基于40纳米CMOS工艺的500-MS/s 10-bit三通道电流舵型DAC的鲁棒性设计

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed.The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design.The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains.The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB.The measured SFDR at 1.7 MHz output signal is 58.91 dB,58.53 dB and 56.98 dB for R/G/B channels,respectively.The DAC has good static and dynamic performance despite the single-ended output.The average rising time and falling time of three channels are 0.674 ns and 0.807 ns.The analog/digital power supply is 3.3 V/1.1 V.This triple-channel DAC occupies 0.5656 mm2.     

A 10-bit 200-MHz CMOS video DAC for HDTV applications

This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm². When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.     

A 12-bit 10-MS/s SAR ADC with a weighted sampling time technique applied to C-DAC

This paper presents a low power 12-bit 10-MS/s successive approximation register (SAR) analog-to-digital convert (ADC) for bio-signal signal processing in wearable sensor systems. A weighted sampling time technique applied to a capacitor digital to analog converter (C-DAC) is employed to reduce the power consumption of the conventional SAR ADC with minimum performance sacrifice. The proposed technique helped reduce its energy consumed by MSB, MSB-1, MSB-6, and MSB-7 capacitors by more than 40% compared with that of the conventional C-DAC. Another technique, a voltage scaling method is also employed to lower the power supply voltage from 1.2 to 0.6 V for all the digital logics except the output registers, such that it results in a power reduction of 70%. The proposed ADC is implemented with the standard CMOS 65 nm 1-poly 6-metal n-well process. The ADC achieves DNL/INL of?±?1.2LSB/?±?1.5LSB, ENOB of 10.3-b, power consumption of 31.2 μW, and Walden FoM of 2.7fJ/step.

     

一种电容阵列结构的10位8通道1MS/s逐次逼近AD转换器

设计了一种用于多电源SoC的10位8通道1MS/s逐次逼近结构AD转换器。为提高ADC精度,DAC采用改进的分段电容阵列结构。为降低功耗,比较器使用了反相器阈值电压量化器,在模拟输入信号的量化过程中减少静态功耗产生。电平转换器将低电压数字逻辑信号提升为高电平模拟信号。采用UMC 55nm 1P6M数字CMOS工艺上流片验证设计。测试结果表明,当采样频率为1 MS/s、输入信号频率为10 kHz正弦信号情况下,该ADC模块在3.3 V模拟电源电压和1.0 V数字电源电压下,具有最大微分非线性为0.5LSB,最大积分非线性为1LSB。测得的SFDR为75 dB,有效分辨率ENOB为9.27位。     

Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

A compact and low power 12-bit 300 MS/s current steering CMOS D/A converter is presented. The architecture of the D/A converter is based on the current steering 6 + 6 segmented type with a laminated current cell relocation technique. In order to improve the linearity and glitch noise, a high output impedance analog current cell is designed. Furthermore, for the purpose of reducing the chip area and power dissipation, a noble merged switching logic and a compact layout technique are proposed. To verify its performance, the chip was fabricated with 0.13 μm thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is 0.26 mm² (510 × 510 μm) with a power consumption of 100 mW. The measured INL and DNL are within ±3LSB and ±1LSB, respectively. The measured SFDR is about 70 dB, when the input frequency is 1 MHz at a clock frequency of 300 MHz.     

一种基于0.35μm CMOS工艺的14位100MSPS DAC设计

基于 TSMC 0 .3 5μm CMOS工艺设计了一种工作电压为 3 V/ 5 V的 1 4位 1 0 0 MSPS DAC。 1 4位DAC在 5 0 Ω负载条件下满量程电流可达 2 0 m A,当采样速率为 1 0 0 MHz时 ,5 V电源的满量程条件下功耗为1 90 m W,而 3 V时的相应功耗为 45 m W该 DAC的积分非线性误差 ( IN L )为± 1 .5 LSB,微分非线性误差( DN L)为± 0 .75 LSB。在 1 2 5 MSPS,输出频率为 1 0 MHz条件下的无杂波动态范围 ( SFDR)为 72 d Bc。     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

A current-steering self-calibration 14-bit 100-MSPs DAC

This paper presents the design and implementation of a 14-bit,100 MS/s CMOS digital-to-analog converter(DAC).Analog background self-calibration based on the concept of analog current trimming is introduced.A constant clock load switch driver,a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance.The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33× 0.97 mm2 of the core area.The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog,respectively.The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB,respectively.The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.     

22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

The Column-Parallel Overlapping-Subrange Successive-Approximation-Register Analog-to-Digital Converter (CPOSSAR ADC) uses a 5-bit split capacitor DAC twice to achieve 9-bit resolution. Its total capacitor area is only 3% of a 9-bit binary weighted DAC and the average switching power is only 12% of a conventional 9-bit DAC. The ADC can perform a 9-bit conversion by first digitizing the 4 most significant bits (MSB) in a coarse conversion stage and then digitizing the 5 least significant bits (LSB) in a fine conversion stage. The accuracy requirement of the DAC is reduced by using overlapping subranges. The proposed ADC achieved an SFDR of 73.6 dB and a SINAD of 55 dB in post-layout simulation, corresponding to an ENOB of 8.8 bits. The design was fabricated in a TSMC׳s 0.35 μm high-voltage process. The use of overlapping subranges reduced the DNL error from +5.14/−1 LSB to +1.27/−0.92 LSB, and improved the INL error from +5.35/−5.34 LSB to +3.17/−3.18 LSB. At a sampling rate of 1.1 MS/s the ADC achieved 41.5 dB SFDR, 34.2 dB SINAD, and consumed 242 μW/channel dynamic power. An individual ADC channel is only 22 μm wide. COPSSAR ADCs are a factor of 4, 2, and 2.5 more area efficient than Multiple-ramp Single-slope ADCs, SAR ADCs, and Cyclic ADCs.     

A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS

A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s. The chip occupies 0.8-mm² active area, fabricated in 0.35-μm CMOS     

A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC

A low voltage-power, 13-bit and 16 MSPS analog-to-digital converter (ADC) was implemented in 0.25-/spl mu/m one-poly five-metal standard CMOS process with MIM capacitors. This ADC used a constant-gm switch to improve the nonlinear effect and a telescopic operational transconductance amplifier with a wide-swing biasing technique for power saving and low supply voltage operation. The converter achieved a peak SNDR of 59.2 dB with 16.384 MSPS, a low supply voltage of 1.3V, and Nyquist input frequency of 8.75 MHz. The static INL of /spl plusmn/2.0 LSB and DNL of /spl plusmn/0.5 LSB were obtained. The total power consumption of this converter was 78 mW. This chip occupied 3.4 mm /spl times/ 3.6 mm area.     

一种用于电流舵DAC的SDR校正技术

提出了一种基于电流舵DAC的SDR校正技术。首先采用拆分电流源的方法,增加了待校正电流源的个数。然后采用动态组合的方式,减小了电流源的失配误差,提高了DAC的静态与动态性能。与DMM校正技术相比,该SDR校正技术具有更小的残余误差、更好的静态与动态性能。采用40 nm CMOS工艺实现了一种14位200 MS/s的电流舵DAC,并进行了仿真。结果表明,通过数字校正,该DAC的INL与DNL分别从1.5 LSB和0.5 LSB降低到0.33 LSB和0.25 LSB,SFDR在整个Nyquist带宽内均大于70 dB。     

A pipeline A/D converter architecture with low DNL

A pipeline analog-to-digital converter architecture can reduce the differential nonlinearity (DNL) with a swapping technique without involving special calibration techniques. An implementation of the overrange stages in the analog pipeline suitable for high-speed applications is proposed. A 14-bit 5-MSample/s converter has been fabricated in a double-poly 0.5-μm CMOS process. The 3.3×3.3 mm ² chip dissipates 320 mW from a single 5 V supply and achieves a signal-to-noise ratio of 79 dB, a dynamic range of 82 dB, and a DNL below 0.4 LSB     

A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2

A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from DC to Nyquist. The measured differential nonlinearity and integral nonlinearity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-μm, single-poly, four-metal, 3.3 V, standard digital CMOS process and occupies 0.6 mm². When operating at 500 MSample/s, it dissipates 125 mW from a 3.3 V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry     

应用于AMOLED源极驱动的高精度DAC设计

针对OLED显示面板更高分辨率、更高精度的需求,本文提出了一种应用于高分辨率AMOLED源极驱动的高精度10bit DAC结构。设计的DAC由6bit的GAMMA校正电阻串DAC及4bit的基于尾电流源插值的输出缓冲器级联构成,达到高精度的同时占用较小的芯片面积。为进一步提高AMOLED驱动的灰阶电压精度,增加了一个DAC斜率可编程单元对线性DAC输出曲线进行进一步调节,以更好地拟合AMOLED显示屏所需的灰阶-电压曲线,此外,输出缓冲器采用尾电流源插值的方法来实现高精度的第二级DAC。在UMC 80nm CMOS工艺下,仿真结果表明设计的DAC的最大INL和DNL分别为0.47LSB、0.24LSB。在10kΩ电阻及30pF电容负载下,DAC电压从最低灰阶到最高灰阶的建立时间为3.38μs。驱动电路可以快速、精确地将图像数据转换为建立在像素电路上的电压,满足分辨率为1080×2 160驱动芯片的应用需求。     

A 4-GS/s 4-bit Flash ADC in 0.18- μm CMOS

A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10^-11 at 4 GS/s.