Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs

Symmetric Dual-k Spacer (SDS) Hybrid FinFETs is a novel device, which combines three significant technologies i.e., 2-D ultra-thin-body (UTB), 3-D FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. For the first time, this article systematically analyzes the impacts of non-rectangular fin shape on various performance metrics of SDS Hybrid FinFETs. Under distinctive inclination fin angles as prescribed by the process technology, the performances of the device at different fin heights are examined. This work evaluates the response of fin tapering as well as fin height on parameters like threshold voltage (V_th), subthreshold slope (SS), on current (I_on), transconductance (g_m), transconductance generation factor (TGF), and total gate capacitance (C_gg) in SDS Hybrid FinFETs. Optimum structural configuration is thus proposed to fabricate the hybrid device in sub-20 nm FinFET architecture.     

LKE and BGI Lorentzian noise in strained and non-strained tri-gate SOI FinFETs with HfSiON/SiO2 gate dielectric

The LKE (Linear Kink Effect) and BGI (Back-Gate-Induced) Lorentzians present in the drain current noise spectra of fully-depleted tri-gate n- and pFinFETs, fabricated on sSOI and SOI substrates with HfSiON/SiO₂ gate dielectric are described.It is shown that the analysis of the parameters of LKE and BGI Lorentzians allows to find the values of (С_eq/m′β²), β and [j_EVB/(m′β)²] where С_eq is the body-source capacitance, m′ ≈ 1, β is the body factor and j_EVB is the density of the EVB current flowing through the gate dielectric.As a result, the following effects were observed for the first time: (i) (С_eq/m′β²) decreases with increasing gate overdrive voltage |V^∗| and depends sub-linearly on the effective fin width W_eff under strong inversion conditions; (ii) in depletion and weak inversion where (С_eq/β²) is independent of |V^∗| the proportionality (С_eq/β²) ∝ W_eff is observed for an effective width W_eff ? 0.87 μm while (С_eq/β²) becomes independent on W_eff for W_eff < 0.87 μm; (iii) the value of β for the FinFETs investigated is higher than for their planar counterparts; (iv) in spite of the fact that strain affects the barrier height at the Si/SiO₂ interface, the EVB current densities j_EVB for sSOI and SOI devices are equal; (v) the values of j_EVB for the HfSiON/SiO₂-devices are much higher than for the HfО₂/SiO₂-ones studied previously. It is also shown that the gate overdrive voltage |V^∗| at which the LKE Lorentzians start to appear is as low as 0.25 V.     

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

Fin Field Effect Transistors (FinFETs) are used for Complementary Metal Oxide Semiconductor applications beyond the 45?nm node of the Semiconductor Industry Association (SIA) roadmap because of their excellent scalability and better immunity to short channel effects. This article examines the impact of high-k dielectrics on FinFETs. The FinFET device performance is analysed for On Current, Off Current, I _on/I _off ratio, drain induced barrier lowering, electrostatic potential along the channel, electric field along the channel, transconductance, output resistance, intrinsic gain, gate capacitance and transconductance generation factor, by replacing the conventional silicon dioxide gate dielectric material, with various high dielectric constant materials. Nanosize ZrO₂ (zirconium-di-oxide) is found out to be the best alternative for SiO₂ (silicon-di-oxide). It is also observed that the integration of high-k dielectrics in the devices significantly reduces the short channel effects and leakage current. The suitability of nanoscale FinFETs is observed with the help of an inverter circuit and their gain values are calculated for circuit applications.     

Suppression of corner effects in wide-channel triple-gate bulk FinFETs

This paper presents a method of eliminating corner effects in triple-gate bulk FinFETs. The parasitic device in FinFET’s corners can be turned off by increasing body doping in corner regions by corner implantation. Corner implantation described in this work does not require additional masks, rotation or tilt. This method is investigated in idealized (with rectangular cross-section of the fin) and realistic (with rounded top corners of the fin) triple-gate bulk FinFETs and has shown considerable improvements: kink effect in transfer characteristics is completely eliminated, threshold voltage increased by up to 0.43 V, subthreshold swing and drain-induced barrier-lowering decreased to values under 95 mV/dec and 16 mV/V, respectively. Optimization is performed on the realistic rounded-corner FinFET structure to find the proper body doping and corner implantation peak values for acceptable threshold voltage and on-state current.     

一种新型高性能FinFET的设计与特性分析

针对CMOS器件随着技术节点的不断减小而产生的短沟道效应和漏电流较大等问题,设计了一种新型直肠形鳍式场效应晶体管(FinFET),并将该新型器件与传统的矩形结构和梯形结构的FinFET通过Sentaurus TCAD仿真软件进行对比。结果表明,当栅极长度控制在10 nm时,新型器件相比于另外两种传统的FinFET具有更小的鳍片尺寸,且鳍片高度不低于抑制短沟道效应的临界值。仿真结果显示,这种新型的FinFET具有更好的开关特性和亚阈值特性。同时,该器件在射频方面的特性参数也显示出该器件具有较高性能,并有一定的实际应用价值。     

FinFET for high sensitivity ion and biological sensing applications

A double-gate (DG) fin field effect transistor (FinFET) is discussed as new label-free ion and biological sensor. Simulations as function of channel doping, geometrical dimensions, operation point and materials investigated the device response to an external potential difference which provides a body threshold voltage modulation. The simulation results presented in this work clearly state the key features for an ultrasensitive FET based sensor: an enhancement low doped and partially gated transistor operating in weak-moderate inversion regime. The optimized sensitivity, obtained when the width of the fin is equal to the gate height (w_NW ∼ h_g), reaches a value of 85% for an extraction current, I_d, of 0.1 μA. These results pave the way for the fabrication process of an innovative CMOS compatible sensing system.     

FinFET器件总剂量效应研究进展

全面综述鳍式场效应晶体管(FinFET)的总剂量效应,包括辐照期间外加偏置、器件的工艺参数、提高器件驱动能力的特殊工艺、源/漏掺杂类型以及不同栅介质材料和新沟道材料与FinFET总剂量效应的关系。对于小尺寸器件,绝缘体上硅(SOI)FinFET比体硅FinFET具有更强的抗总剂量能力,更适合于高性能抗辐照的集成电路设计。此外,一些新的栅介质材料和一些新的沟道材料的引入,如HfO₂和Ge,可以进一步提高FinFET器件的抗总剂量能力。     

Study on the performance of sub 100 nm LACLATI MOSFETs for digital application

With the help of extensive simulations, we systematically investigated the effects of varying tilt angle of halo implant in sub 100 nm lateral asymmetric channel (LAC) MOSFETs on the reverse short channel effects, the on current and the hot carrier immunity. The devices with large angle tilt implants also show the substantial reduction in the subthreshold swing, improvement in I_ON/I_OFF ratio and significantly the lower junction capacitance as compared to the devices with low angle tilt implant. It is also observed that the subthreshold characteristics do not change as the channel length decreases for such devices. These devices, known as lateral asymmetric channel with large angle tilt implant (LACLATI), will therefore have much improved performance in comparison to a low angle tilt implant LAC devices for digital applications.     

Work Function Tuning and Doping Optimization of 22-nm HKMG Raised SiGe/SiC Source–Drain FinFETs

The basic requirements on process design of extremely scaled devices involve appropriate work function and tight doping control due to their significant effect on the threshold voltage as well as other critical electrical parameters such as drive current and leakage. This paper presents a simulation study of 22-nm fin field-effect transistor (FinFET) performance based on various process design considerations including metal gate work function (WF), halo doping (N _halo), source/drain doping (N _sd), and substrate doping (N _sub). The simulations suggest that the n-type FinFET (nFinFET) operates effectively with lower metal gate WF while the p-type FinFET (pFinFET) operates effectively with high metal gate WF in 22-nm strained technology. Further investigation shows that the leakage reduces with increasing N _halo, decreasing N _sd, and increasing N _sub. Taguchi and Pareto analysis-of-variance approaches are applied using an L₂₇ orthogonal array combined with signal-to-noise ratio analysis to determine the best doping concentration combination for 22-nm FinFETs in terms of threshold voltage (V _t), saturation current (I _on), and off-state current (I _off). Since there is a tradeoff between I _on and I _off, the design with the nominal-is-best V _t characteristic is proposed, achieving nominal V _t of 0.259 V for the nFinFET and ?0.528 V for the pFinFET. Pareto analysis revealed N _halo and N _sub to be the dominant factor for nFinFET and pFinFET performance, respectively.     

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.     

Quantum-mechanical effects and gate leakage current of nanoscale n-type FinFETs: A 2d simulation study

This paper simulates a kind of new sub-50 nm n-type double gate MOS nanotransistors by solving coupled Poisson-Schrödinger equations in a self-consistent manner with a finite element method, and presents a systematic simulation-based study on quantum-mechanical effects, gate leakage current of FinFETs. The simulation results indicate that the deviation from the classical model becomes more important as the gate oxide, gate length and Fin channel width becomes thinner and the Fin channel doping increases. Gate tunneling current density reduces with the body thickness decreasing. Excessive scaling increases the gate current below Fin thickness of 5 nm. The gate current can be dramatically reduced beyond 10¹⁷ cm⁻³ with the Fin body doping increasing. In order to understand the influence of electron confinement, quantum mechanical simulation results are also compared with the results from the classical approach. Our simulation results indicate that quantum mechanical simulation is essential for the realistic optimization of the FinFET structure.     

The meta-stable dip (MSD) effect in SOI FinFETs

The meta-stable dip (MSD) effect is demonstrated and characterized in SOI FinFETs. With ascending scan of front-gate voltage (V_G1), the magnitude of drain current (I_D) tends to be fixed within a specific region of the front-gate voltage and this leads to a dip of transconductance (g_m). The dip width can be modulated through a control of bias condition or measurement speed such as back-gate voltage (V_G2), drain voltage (V_D) and step size of the front-gate voltage. From the dual-gate transient measurement, it is found that the MSD effect is highly dependent on the floating-body effect. In SOI FinFETs, the MSD effect is significantly affected by the fin width due to the fringing electric field of the lateral gates.     

Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

We propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage V _th, channel length L and gate oxide thickness t _ox are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm technology.     

Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs

The impact of the spacer length at the source (L_s) and drain (L_d) on the performance of symmetrical lightly-doped double-gate (DG) MOSFET with gate length L = 20 nm is analyzed, with the type and doping concentration of the spacers kept the same as in the channel material. Using the transport parameters extracted from experimental data of a double-gate FinFET, simulations were performed for optimization of the underlapped gate-source/drain structure. The simulation results show that the subthreshold leakage current is significantly suppressed without sacrificing the on-state current for devices designed with asymmetrical source/drain extension regions, satisfying the relations L_s = L/2 and L_d = L. In independent drive configuration, the top-gate response can be altered by application of a control voltage on the bottom-gate. In devices with asymmetrical source/drain extension regions, simulations demonstrate that the threshold voltage controllability is improved when the drain extension region length is increased.     

FinFET based SRAM bitcell design for 32 nm node and below

The methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves consideration of both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V_ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell <0.1 μm² below 32 nm node.     

Reduction of gate-to-channel tunneling current in FinFET structures

In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO₂ than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6 nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25 nm. The possible reasons for the observed effect are discussed.     

Device and circuit level suppression techniques for random-dopant-induced static noise margin fluctuation in 16-nm-gate SRAM cell

In this study, a three-dimensional “atomistic” coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are further implemented to examine the associated characteristics in 16-nm-gate SRAM cells. From the circuit viewpoint, the SNM of 8T planar SRAM is enlarged to 230 mV and the variation of SNM (σ_SNM) is reduced to 22 mV at a cost of 30% extra chip area. As for device level improvement, silicon-on-insulator (SOI) FinFETs replaced the planar MOSFETs in 6T SRAM is further examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the σ_SNM is suppressed significantly to 5.4 mV. However, development of fabrication process for SOI FinFET SRAM is crucial for sub-22 nm technology era.     

Implications of fin width scaling on variability and reliability of high-k metal gate FinFETs

In this paper, we report a study to understand the fin width dependence on performance, variability and reliability of n-type and p-type triple-gate fin field effect transistors (FinFETs) with high-k dielectric and metal gate. Our results indicate that with decreasing fin width the well-known performance improvement in terms of sub-threshold swing and drain-induced barrier lowering are accompanied by a degradation of the variability and the reliability. As a matter of fact fin width scaling causes (i) higher hot-carrier degradation (HC) in nFinFETs owing to the higher charge carrier temperature for the same internal stress voltages; (ii) worse negative bias temperature instability (NBTI) in pFinFETs due to the increased contribution from the (1 1 0) surface; (iii) higher variability due to the non-uniform fin extension doping, as highlighted by applying a novel characterization technique.     

Performance characteristics of <Emphasis Type="Italic">p</Emphasis>-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

The length of Source/Drain (S/D) extension (L_SDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer L_SDEpFinFET provides a larger series resistance and degrades the drive current (I_DS), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter L_SDE plus the shorter channel length demonstrates a higher trans-conductance (G _m ) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer L_SDE represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current.     

Analysis of 14nm technology node In0.53Ga0.47As nFinFET integrated with In0.52Al0.48As cap layer for high-speed circuits

CMOS (Complementary Metal-oxide-semiconductor) based high-speed applications in the sub-14 nm technology node using InGaAs Fin field-effect-transistors (FinFETs) confront with inevitable effect in form of interface traps upon integration of dielectric layer with InGaAs material. In this work, we have explored the impact of the traps on short channel effects (SCEs) and a technique of abating the effect of interface traps by introducing In_0.52Al0.₄₈As cap layer. Proposed work reforms the device by varying the cap layer thickness (Tcap), doping concentrations of cap layer and underlap region. The effect of traps on intrinsic delay, work function variation and SCEs was investigated to assess the trend on devices with In_0.52Al_0.48As cap layer. It has been observed that introduction of Tcap improves SCEs and helps to mitigate the effect of interface traps. SCEs can be additionally diminished by presenting underlap fin length at the cost of higher delay. The experimental results show the value of subthreshold swing = 149.54 mV/decade, drain-induced barrier lowering = 38.5 mV V^?1 and delay = 1.1 ps for T_cap = 4 nm without underlap fin length structure for traps concentration of 10¹² cm^?2eV^?1. Thus, significant improvement has been seen in SCEs and delay performance in FinFET structure with cap layer.