Electrical reliability aspects of HfO2 high-k gate dielectrics with TaN metal gate electrodes under constant voltage stress

The dielectric breakdown property of ultrathin 2.5 and 5.0 nm hafnium oxide (HfO₂) gate dielectric layers with metal nitride (TaN) gate electrodes for metal oxide semiconductor (MOS) structure has been investigated. Reliability studies were performed with constant voltage stressing to verify the processing condition effects (film thicknesses and post metal annealing temperatures) on times to breakdown. The leakage current characteristics are improved with post metal annealing temperatures (PMA) for both 2.5 and 5.0 nm HfO₂ physical thicknesses. However, it is more prominent (2 orders of magnitudes) for 2.5 nm HfO₂ film thickness. The values of oxide-trapped charge density and interface-state density are also improved for 2.5 nm HfO₂ film. The different stages of charge-trapping behaviors, i.e., stress-induced leakage current, soft and hard breakdown mechanisms have been detected. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate current is observed, followed by the occurrence of several fluctuations. The amplitude of the fluctuations is much larger in the 5.0 nm HfO₂ gate dielectric layer compared to the 2.5 nm HfO₂ layer. After the occurrence of such fluctuations, the current–voltage characteristics exhibited an increased in gate current compared to the fresh (unstressed) devices.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Self-aligned n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using HfO2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO₂/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm²/V s) with high temperature PMA (950 °C, 1 min) and good inversion.     

Effect of RuO2 electrode on laser-MBE prepared HfO2 gate dielectrics

In this paper, we report our recent study of the effect of RuO₂ as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO₂, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO₂ for pMOS devices. Structural, dielectric and electric properties were investigated. RuO₂/HfO₂/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm⁻¹). Compared to the SiO₂ dielectric with the same EOT value, RuO₂/HfO₂/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO₂ top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 10¹² cm⁻². All the results above indicate that RuO₂ is a promising alternative gate electrode for LMBE grown HfO₂ gate dielectrics.     

低温退火对具有HfO2/TiN栅结构的MOS电容电学性能的影响

The effects of low temperature annealing,such as post high-k dielectric deposition annealing(PDA),post metal annealing(PMA)and forming gas annealing(FGA)on the electrical characteristics of a metal–oxide–semiconductor(MOS)capacitor with a TiN metal gate and a HfO2dielectric are systematically investigated.It can be found that the low temperature annealing can improve the capacitance–voltage hysteresis performance significantly at the cost of increasing gate leakage current.Moreover,FGA could effectively decrease the interfacial state density and oxygen vacancy density,and PDA could make the flat band positively shift which is suitable for P-type MOSs.     

Preparation of conductive HfN by post rapid thermal annealing-assisted MOCVD and its application to metal gate electrode

Conductive hafnium nitride (HfN) with negligible carbon impurity (<0.1 at.%) was chemically synthesized for the first time by post-rapid thermal annealing (PRTA)-assisted metal organic chemical vapor deposition (MOCVD) method. The thermodynamic instability of N-rich hafnium nitride (Hf₃N₄) phase, which is considered to be the dominant phase in CVD deposition of hafnium nitride, was utilized for pure and metallic HfN synthesis. By integrating the PRTA-HfN film into MOS capacitor, the electrical properties of the PRTA-HfN film as metal gate electrode were studied. Well behaved electrical characteristics such as about 4.9 eV of effective work function, low leakage current and large reduction in SiO₂ equivalent oxide thickness (EOT), which was attributed to the combination of physical thinning of SiO₂ and formation of high-κ interfacial layer, suggest the potential capability of PRTA-assisted MOCVD in chemically synthesizing HfN metal gate electrode for pMOS devices application.     

Impact of the TiN electrode deposition on the HfO2 band gap for advanced MOSFET gate stacks

The impact of the deposition of a TiN electrode on the high-k oxide HfO₂ has been investigated, focussing on the dielectric band gap. After the gate elaboration, a non-destructive approach combining Spectroscopic Ellipsometry (SE), Reflection Electron Energy Loss Spectroscopy (REELS) and X-ray Photoelectron Spectroscopy (XPS) was developed to probe the buried metal/high-k interface. The overall optical band gap is 5.9 ± 0.1 eV with no change after the metal gate deposition. A local reduction of 1 eV is measured near the TiN layer, due to N diffusion at the interface creating N 2p states at the top of the HfO₂ valence band. Increased disorder and defects are identified in the high-k after gate elaboration by XPS, REELS and SE.     

Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO2 transistors

The effects of pre-deposition substrate treatments and gate electrode materials on the properties and performance of high-k gate dielectric transistors were investigated. The performance of O₃ vs. HF-last/NH₃ pre-deposition treatments followed by either polysilicon (poly-Si) or TiN gate electrodes was systematically studied in devices consisting of HfO₂ gate dielectric produced by atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) using X-ray spectra and Electron Energy Loss Spectra (EELS) were used to produce elemental profiles of nitrogen, oxygen, silicon, titanium, and hafnium to provide interfacial chemical information and to convey their changes in concentration across these high-k transistor gate-stacks of 1.0–1.8 nm equivalent oxide thickness (EOT). For the TiN electrode case, EELS spectra illustrate interfacial elemental overlap on a scale comparable to the HfO₂ microroughness. For the poly-Si electrode, an amorphous reaction region exists at the HfO₂/poly-Si interface. Using fast transient single pulse (SP) electrical measurements, electron trapping was found to be greater with poly-Si electrode devices, as compared to TiN. This may be rationalized as a result of a higher density of trap centers induced by the high-k/poly-Si material interactions and may be related to increased physical thickness of the dielectric film, as illustrated by HAADF-STEM images, and may also derive from the approximately 0.5 nm larger EOT associated with polysilicon electrodes on otherwise identical gate stacks.     

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

Characteristics and thermal stability of MOS devices with MoN/TiN and TiN/MoN metal gate stacks

Metal gate with high work function is the key issue for MOS device. The influences of MoN metal gate with TiN layer above or below and various post metal annealing (PMA) treatments were studied in this work. Experimental results show that metal gate stack with TiN under MoN film (i.e., MoN/TiN sample) exhibits better electrical characteristics on gate leakage current, stress-induced flat-band voltage shift, and stress-induced leakage current and thermal stability despite a little lower work function. Thus MoN/TiN metal gate is promising for p-channel MOS device applications.     

Role of lanthanum in the gate stack: Co-sputtered TaLaN metal gates on Hf-based dielectrics

We examine the characteristics of TaLaN metal gates in direct contact with HfO₂ dielectric, in particular focusing on the effect of La in the gate stack for NMOS applications. Effective work functions (EWF) and vacuum work functions (WF) are measured as a function of lanthanum content in TaLaN without any intentional heating using X-ray photoelectron spectroscopy, U-V photoelectron spectroscopy, and electrical C-V measurements. We find that the addition of lanthanum to tantalum nitride lowered both the EWF and the WF of the metal gate by ∼0.2 eV and ∼0.9 eV, respectively. Furthermore, XPS indicates that lanthanum in TaLaN at the interface with HfO₂ is primarily bonded to nitrogen rather than oxygen and not reacting with the dielectric.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric

An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found to have lower interface trap density. Thicker TiN, however, showed better barrier properties for impurity diffusion from the polysilicon-capping layer. We found that 10 nm is the optimum thickness of the ALD TiN layer for minimizing charge trapping and adequate blocking of boron penetration.     

CMOS compatible dual metal gate integration with successful Vth adjustment on high-k HfTaON by high-temperature metal intermixing

In this paper, we report for the first time a novel dual metal gate (MG) integration process for gate-first CMOS platform by utilizing the intermixing (InM) of laminated ultra-thin metal layers during high-temperature annealing at 1000 °C. In this process, an ultra-thin (2 nm) TaN film is first deposited on gate dielectric as a buffer layer. Preferable laminated metal stacks for NMOS and PMOS are then formed on a same wafer through a selective wet-etching process in which the gate dielectric is protected by the TaN buffer layer. Dual work function for CMOS can finally be achieved by the intermixing of the laminated metal films during the S/D activation annealing. To demonstrate this process, prototype metal stacks of TaN/Tb/TaN (NMOS) and TaN/Ti/HfN (PMOS) has been integrated on a single wafer, with WF of 4.15 and 4.72 eV achieved, respectively. Threshold voltage (V_th) adjustment and transistor characteristics on high-k HfTaON dielectric are also studied.     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.     

The effect of oxygen in Ru gate electrode on effective work function of Ru/HfO2 stack structure

Effective work function (φ_m,eff) values of Ru gate electrode on SiO₂ and HfO₂ MOS capacitors were carefully examined and discussed from the viewpoint of an effect of oxygen incorporation in Ru gate electrode on φ_m,eff. Annealing at 400 °C in the reduction (3%H₂) and the oxidation (1%O₂) ambient resulted in similar changes in the φ_m,eff of Ru/HfO₂/SiO₂ and Ru/SiO₂ MOS capacitors. Furthermore, the Ru gate MOS capacitor after annealing in the oxidation condition have shown almost the same φ_m,eff value to that of RuO₂ gate MOS capacitors. The oxygen concentration in the Ru/HfO₂ interface after annealing in oxidizing atmosphere is approximately one order of magnitude higher than that after annealing in reducing atmosphere as confirmed by secondary ion mass spectroscopy analysis. Furthermore, the higher oxygen concentration at the Ru/dielectric interface leads to the higher φ_m,eff value, regardless of SiO₂ or HfO₂ dielectrics. This indicates that φ_m,eff of Ru gate MOS capacitor is dominantly determined by the oxygen concentration at the Ru/dielectric layer interface rather than the dipoles originated from the oxygen vacancy in HfO₂.     

采用电子束蒸发方法结合一步快速退火制备的Ni-FUSI栅性能研究

本文采用高真空电子束蒸发方法在HfO2栅介质上依次沉积了Si膜与Ni膜并结合一步快速退火制备了Ni基全硅化物金属栅（Ni-FUSI)。X射线衍射和拉曼光谱结果表明经过快速退火处理金属栅完成了硅化反应其主相为镍硅化物相。我们通过制备Ni-FUSI/ HfO2 /Si结构(MIS)电容研究了NiSi栅的电学性能。测得的C-V曲线积累区曲线平坦,从积累区到反型区界面陡峭,滞回电压很小,提取的NiSi功函数为5.44eV~5.53eV。MIS电容漏电流很小,在栅压为-1V时漏电流密度只有1.45?10-8A/cm-2。     

Drain current enhancement and negligible current collapse in GaN MOSFETs with atomic-layer-deposited HfO2 as a gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect-transistors (MOSFET’s) with atomic-layer-deposited HfO₂ gate dielectrics have been fabricated; a 4 μm gate-length device with a gate dielectric of 14.8 nm in thickness (an equivalent SiO₂ thickness of 3.8 nm) gave a drain current of 230 mA/mm and a broad maximum transconductance of 31 mS/mm. Owing to a low interfacial density of states (D_it) at the HfO₂/GaN interface, more than two third of the drain currents come from accumulation, in contrast to those of Schottky-gate GaN devices. The device also showed negligible current collapse in a wide range of bias voltages, again due to the low D_it, which effectively passivate the surface states located in the gate-drain access region. Moreover, the device demonstrated a larger forward gate bias of +6 V with a much lower gate leakage current.     

Annealing effect on the metal gate effective work function modulation for the Al/TiN/SiO2/p-Si structure

In this work, the thermal annealing effect on the metal gate effective work function (EWF) modulation for the Al/TiN/SiO₂/p-Si(1 0 0) structure was investigated. Compared with the sample of TiN/SiO₂/p-Si(1 0 0) structure, for the sample additionally capped with Al the flat band voltage has a very obvious shift as large as 0.54 V to the negative direction after forming gas annealing. It is also revealed that the thermal budget can effectively influence both the EWF of the gate electrode and the thickness of the gate dielectric layer when a post annealing at 600 °C with different soak times was applied to the samples with Al cap. Material characterization indicates that the diffusion of Al and the formation of Al oxide during annealing should be responsible for all the phenomena. The interface trap density Dit calculated from the high-frequency C-V and the laser-assisted high-frequency C-V curves show that the introduction of Al does not cause reliability problem in the Al/TiN/SiO₂/p-Si structure.     

Characteristics of metal-oxide-semiconductor (MOS) device with Er metal gate on SiO2 film

We have investigated the structural and electrical properties of metal-oxide-semiconductor (MOS) devices with Er metal gate on SiO₂ film. Rapid thermal annealing (RTA) process leads to the formation of a high-k Er-silicate gate dielectric. The in situ high-voltage electron microscopy (HVEM) results show that thermally driven Er diffusion is responsible for the decrease in equivalent oxide thickness (EOT) with an increase in annealing temperature. The effective work function (Φ_m,eff) of Er metal gate, extracted from the relations of EOT versus flat-band voltage (V_FB), is calculated to be ∼2.86 eV.