A step-and-repeat UV-nanoimprint lithography process using an elementwise patterned stamp

Ultraviolet-nanoimprint lithography (UV-NIL) is a promising cost-effective method for defining nanoscale structures at room temperature and low pressure. To apply a large-area stamp to a high throughput step-and-repeat process at atmospheric conditions, we proposed a new UV-NIL process that uses an elementwise patterned stamp (EPS), which consists of elements separated by channels, and additive gas pressurization. The proposed UV-NIL process required just four imprints to press an 8-in. wafer. EPS features measuring 50-80 nm were successfully transferred onto the wafers. The experiments demonstrated that a 5 × 5-in.² EPS could be used with a step-and-repeat UV-NIL process to imprint 8-in. wafers under atmospheric conditions.     

Fabrication of a two-step Ni stamp for blind via hole application on PWB

This study examined imprint lithography with a two-step Ni stamp to solve the laser process problems and simultaneously form a blind via and layer pattern. The Ni stamp was fabricated by electroplating on a dry-etched Si mold, made from a SOI (silicon on insulator) wafer, and pattern replication. For the pattern transfer of the Ni stamp, hot embossing was performed on SU8-coated BT and Si wafer substrates. The residual layer was of a uniform thickness with an embossed shape of acceptable squareness.     

Large area nanosize array stamp for UV-based nanoimprint lithography fabricated by size reduction process

A novel size reduction process using electron beam lithography (EBL) combining with wet etching technique is developed as a possible solution for producing large area and low cost nanopattern stamp for UV-based nanoimprint lithography (UV-NIL). In the first step, a microstructure stamp with 1.4 μm periodical pore array and aspect ratio of 1:1 was formed over a 1 inch² area on a quartz substrate. This process was carried out using common electron beam lithography (EBL) equipment, which was easily available in the modern integrated circuits (IC) semiconductor factory. Afterwards, with a controlled wet etching technique, the pore array was changed into tip patterns with the line width below 100 nm and the period keeping as before. The uniformities and nanopattern accuracies were investigated to identify its possibility as a UV-NIL stamp by AFM and SEM. Finally, as a demonstration, the as obtained stamp was used as a positive stamp to replicate the nanotips into UV-curable resist successfully by a UV-NIL process. The method developed for the mold of nanoimprint lithography would be a simple and low price approach to fabricate large area UV-NIL stamp and the nanotip array structures would be widely used in two dimensional (2D) photonic crystal application.     

A mathematical model for slip phenomenon in a cavity-filling process of nanoimprint lithography

Squeeze flow theory has been used as an effective tool to clarify how and which process conditions determine cavity-filling behavior in nanoimprint lithography (NIL). Conventional squeeze flow models used in NIL research fields have assumed no-slip conditions at the solid-to-liquid boundaries, that is, at the stamp-to-polymer or polymer-to-substrate boundaries. The no-slip assumptions are often violated, however, in micrometer- to nanometer-scale fluid flow. It is therefore necessary to adopt slip or partial slip boundary conditions. In this paper, an analytical mathematical model for the cavity-filling process of NIL that takes into account slip or partial slip boundary conditions is derived using squeeze flow theory. Velocity profiles, pressure distributions, imprinting forces, and evolutions of residual thickness can be predicted using this analytical model. This paper also aims to elucidate how far the slip phenomenon is able to promote the process rate.     

A novel loading and demoulding process control in UV nanoimprint lithography

In UV nanoimprint lithography (NIL) with elastic mould, a novel multi-step loading and demoulding process, called distortion reduction by pressure releasing (DRPR) and two-step curing method for demoulding, is developed. This novel imprint process is continuous, the pressure releasing method, used to optimize the loading process, can reduce the distortions of imprint mould and wafer stage, while obtain better cavity filling and thin and uniform residual layer; through two-step curing method instead of traditional simple demoulding, the curing degree of resist can be controlled, which is helpful to decrease the demoulding force and avoid residual layer pulled-up while ensure replicated protrusions not collapse. It is a novel and robust process with high fidelity of pattern replication in micro/nano structures fabrication, and the replication error caused by distortions and “blind” demoulding can be reduced effectively.     

Press and release imprint: Control of the flexible mold deformation and the local variation of residual layer thickness in soft UV-NIL

We report on a two step soft UV nanoimprint process termed “Press and Release Imprint (PRI) that enables the reduction of both the mold deformation and the local variation of the residual layer thickness, thereby allowing high fidelity pattern replication with a uniform local residual layer thickness. The effect of imprint pressure on the mold deformation, local variation of residual layer thickness as well as required mold release time has been investigated for microscale patterns in the range of 10-100 μm. The potentials of PRI are demonstrated by high fidelity replication of micro-patterns with a uniform residual layer of minimum thickness.     

空气中烧成镍电极浆料的研究

介绍了空气中烧成的Ni电极浆料的制备。讨论了浆料中玻璃粉、硼粉含量及烧渗工艺等对电极性能的影响。结果表明:浆料中Ni粉的纯度应为99.5%,粒度为500目;w(Ni)应不低于65%;玻璃粉的软化温度为450℃左右;粒度为300目,w(玻璃)为20%左右。加入硼粉系作为抗氧化剂。于810℃的大气中烧渗,保温5 min,此贱金属镍电极可牢固地附着在陶瓷基体上,并具有良好的欧姆接触性能。     

Electroless Ni/Immersion Au interconnects: Investigation of black pad in wire bonds and solder joints

Black Pad was observed on Electroless Ni/Immersion Au (ENIG) wire bond pads. Thick immersion Au on highly corroded electroless Ni was detected. It was determined that the pads were electrically connected to the Cu ground plane due to a Ni bridge formed inside normally open photovias. The mechanism of the bridge formation was verified and preventative actions were taken; it was demonstrated that formation of Black Pad could be switched on and off. The mechanism of Black Pad formation is proposed to be defective ENIG plating involving variation of both the electroless Ni and immersion Au plating processes. The intermetallic structures of solder joints on the above pads were studied. The study was conducted on both defective and non-defective pads to show differences in intermetallic structure and composition. Me₂Sn₄ and Me₂Sn₂ (Me=Cu, Ni, and Au) intermetallics were formed on non-defective pads, which nucleated on the Ni layer and grew inside the molten solder. However, only the Me₃Sn intermetallic was formed on defective pads inside the corroded Ni Layer. Both mechanisms of intermetallic formation were found on pads with mildly corroded Ni and intermediate Au thickness (4.5–7 in).     

A novel overlay process for imprint lithography using load release and alignment error pre-compensation method

As a low-cost and high-efficiency alternative to conventional photolithography, imprint lithography has been paid serious attention for it can realize the pattern transfer easily and repeatedly. Even so, there is still a long way to go before this technique can be used to manufacture ICs since the layer-to-layer alignment is a main obstacle. In this paper, the pattern distortion and position shift induced by loading force and friction force are investigated and an optimized process is proposed to realize high precision overlay, in which an optimal loading force and a load release and an alignment error pre-compensation (LRAEPC) method are adopted. The optimal loading force is acquired by comparing the variety trends of the residual layer and position shift with the loading force. Using the optimal loading force, transferred patterns with proper resist thickness and the minimal distortion are achieved. In LRAEPC method, load release is used to correct the pattern distortion and to alleviate the position shift. To avoid subsequent position adjustment in the fluid after load release, the pre-compensation alignment is performed before the mold is in contact with the wafer. This process does not locate correct alignment position and there is an alignment compensation value determined by the statistical data of alignment position shift after load release. Using this pre-compensation alignment method, the correct alignment can be obtained after load release.     

Optimization of process conditions for the formation of hemispherical-grained (HSG) silicon in high-density DRAM capacitor

We have compared the capacitances of a conventional stacked capacitor and hemispherical-grained silicon (HSG-Si), in which the seeding method was applied to storage electrode of 64 Mbit dynamic random access memory (DRAM) through Si₂H₆-molecule irradiation and annealing for HSG-Si formation. Also, we considered the variation of the HSG-Si thickness due to the phosphorus concentration of storage poly-silicon in process condition and the effect of its thickness on the cell capacitance and failure occurrence, etc. We investigated the effect of the deposition temperature of amorphous poly-silicon on the HSG-Si formation. As a result, the optimum process conditions of the phosphorus concentration, the deposition temperature of storage poly-silicon and the HSG thickness in HSG formation are 3.5–4.5×10¹⁹ atoms/cm³, 530°C and 450 Å, respectively. It is found that the limit thickness of dielectric film of 64 Mbit DRAM capacitor according to the optimized process condition is 65 Å.     

A Load-Balancing and Push-Out Scheme for Supporting QoS in MANETs

Currently, mobile ad hoc networks (MANETs) lack load-balancing capabilities, and thus, they fail to provide good performance especially in the case of a large volume of traffic. Ad hoc networks lack also service differentiation. However, in these wireless environments, where channel conditions are variable and bandwidth is scarce, the differentiated services developed for the Internet are suboptimal without lower layers' support. The IEEE 802.11 standard for Wireless LANs is the most widely used WLAN standard today. It has a mode of operation that can be used to provide service differentiation, but it has been shown to perform badly. In this paper, we present a simple but very effective method for support Quality of Service, by the use of load-balancing and push-out scheme. This approach offers to the mobile node: the ability to alleviate congestion by traffic distribution of excessive load, and to support priority of packets in the single MAC buffer. We evaluate the performance of our algorithm and compare it with the original IEEE 802.11b protocol. Simulation results show that this new approach reduces packet loss rate and increases throughput as well as provides service differentiation in the MAC layer.     

一种新的MOS结构量子化效应修正模型

从载流子在 MOS结构反型层内的经典分布和量子化后的子带结构出发 ,提出了经典的和量子化的表面有效态密度 (SL EDOS:Surface layer effective density- of- states)的概念。利用表面有效态密度的概念建立了经典理论框架和量子力学框架内的电荷分布模型。该模型包含了强反型区表面电势的变化对载流子浓度的影响 ,具有很高的计算效率和稳定性。在模型基础上 ,研究了量子化效应对反型层载流子浓度和表面电势的影响。     

A Cross Layer Scheduling Framework for Supporting Bursty Data Applications in WCDMA Networks

In future wireless networks multimedia applications are expected to finally dominate the overall traffic volume. Shared channels are more suitable for the transmission of this type of traffic, as they are able to periodically adjust their transmission rate. In this paper, we introduce a cross-layer framework for WCDMA based networks which aims to make the packet scheduling procedure more efficient. In addition to that, we further propose a traffic scheduling scheme which serves the connections not only according to their delay sensitivity, but also according to the predicted state of their wireless channel. The efficiency of the proposed scheme, in terms of average packet delay and channel utilization is verified via simulations.     

A facile approach to fabricate solution-processable metal oxides for interfacial layer in polymer solar cells

We report a facile approach to prepare metal oxides for the interfacial layer in polymer solar cells (PSCs), in which the precursor solutions were obtained by dissolving commercial metal oxide/hydroxide in ammonia water. This approach can be adopted as a general method to prepare various solution-processable metal oxides for interfacial layers in PSCs, such as MoO_x, VO_x, WO_x and ZnO_x. The photovoltaic performance of PSCs buffered by these metal-oxide layers was studied and the applicability of these interfacial layers was demonstrated both with P3HT and a low band-gap polymer PBDT-T8-TPD.     

A Generalized Analytical Framework for SMPT in a Multicode CDMA Wireless System

Simultaneous MAC Packet Transmission (SMPT) has recently been proposed for stabilizing the throughput over wireless links, which is one of the key challenges in providing high-quality wireless multimedia services. SMPT stabilizes the wireless link by transmitting multiple packets on multiple CDMA channels in parallel in response to packet drops due to wireless link errors. These parallel packet transmissions stabilize the link layer throughput, but they also increase the interference level in a given cell of a cellular network or cluster of an ad-hoc network, which in turn reduces the number of traffic flows that can be simultaneously supported in a cell/cluster. We have recently developed an analytical framework for the class of SMPT mechanisms for a simple Bernoulli packet generation process, which does not reflect the oftentimes bursty packet generation processes encountered in real networks. In this paper we develop a generalized analytical framework for SMPT, which accommodates bursty packet traffic (and also non-bursty Bernoulli traffic). This framework expresses the system dynamics in transition probabilities for a Markov chain and calculates the effects of the interference through an iterative approach. The numerical results from our analytical framework and verifying simulations indicate that SMPT provides a significant reduction in packet loss and buffer occupancies (and delay), especially for persistent traffic bursts, in exchange for a reduced number of supported flows. Our analytical framework quantifies these system trade-offs with good accuracy and can thus be employed for resource management.Manjunath Krishnam received the B.E. degree in Electronics and Communications from R.V. College of Engineering, Bangalore University, Bangalore, India, in 1996, the M.S. degree and Ph.D. degree in Electrical Engineering from Arizona State University, Tempe, AZ, in 1999 and 2004 respectively. His research interests are in the areas of network performance analysis, network and traffic modeling, and resource management in wireless networks. Mr. Krishnam is a member of IEEE.Martin Reisslein is an Assistant Professor in the Department of Electrical Engineering at Arizona State University, Tempe. He is affiliated with ASUs Wireless Integrated Nano Technologyy (WINTech) center. He received the Dipl.-Ing. (FH) degree from the Fachhochschule Dieburg, Germany, in 1994, and the M.S.E. degree from the University of Pennsylvania, Philadelphia, in 1996. Both in electrical engineering. He received his Ph.D. in systems engineering from the University of Pennsylvania in 1998. During the academic year 1994–1995 he visited the University of Pennsylvania as a Fulbright scholar. From July 1998 through October 2000 he was a scientist with the German National Research Center for Information Technology (GMD FOKUS), Berlin. While in Berlin he was teaching courses on performance evaluation and computer networking at the Technical University Berlin. He is editor–in–chief of the IEEE Communications Surveys and Tutorials and has served on the Technical Program Committees of IEEE Infocom, IEEE Globecom, and the IEEE International Symposium on Computer and Communications. He has organized sessions at the IEEE Computer Communications Workshop (CCW). He maintains an extensive library of video traces for network performance evaluation, including frame size traces of MPEG–4 and H.263 encoded video, at He is co–recipient of the Best Paper Award of the SPIE Photonics East 2000—Terabit Optical Networking conference. His research interests are in the areas of Internet Quality of Service, video traffic characterization, wireless networking, and optical networking.     

Optimizations of a photoresist coating process for photolithography in wafer manufacture via a radial basis neural network: A case study

This investigation applied a hybrid method, which combined a trained radial basis network (RBN) [S. Chen, C.F.N. Cowan, P.M. Grant. Orthogonal least squares learning algorithm for radial basis function networks. Neural Networks 2(2) (1991), 302-309] and a sequential quadratic programming (SQP) method [R. Fletcher, Practical Methods of Optimizations, vol. 1, Unconstrained Optimization, and vol. 2, Constrained Optimization, John Wiley and Sons Inc., New York, 1981], to determine an optimal parameter setting for photoresist (PR) coating processes of photolithography in wafer manufacture. Nine experimental runs based on an orthogonal array table were utilized to train the RBN and the SQP method was applied to search for an optimal setting. An orthogonal array table provided an economical and systematic arrangement of experiments to map the relationship between controlled parameters and desired outputs. In this study, a mean thickness and non-uniformity of the thickness of the PR were selected as monitored quality targets for the PR coating process. In addition, the PR temperature, the chamber humidity, the spinning rate, and the dispensation rate were four controlled parameters. The PR temperature and the chamber humidity were found to be the most significant factors in the mean thickness and non-uniformity of the thickness for the PR coating process from the analysis of variance (ANOVA).     

A 3‐in‐1 doping process for interdigitated back contact solar cells exploiting the understanding of co‐diffused dopant profiles by use of PECVD borosilicate glass in a phosphorus diffusion

Boron and phosphorus doping of crystalline silicon using a borosilicate glass (BSG) layer from plasma‐enhanced chemical vapor deposition (PECVD) and phosphorus oxychloride diffusion, respectively, is investigated. More specifically, the simultaneous and interacting diffusion of both elements through the BSG layer into the silicon substrate is characterized in depth. We show that an overlying BSG layer does not prevent the formation of a phosphorus emitter in silicon substrates during phosphorus diffusion. In fact, a BSG layer can even enhance the uptake of phosphorus into a silicon substrate compared with a bare substrate. From the understanding of the joint diffusion of boron and phosphorus through a BSG layer into a silicon substrate, a model is developed to illustrate the correlation of the concentration‐dependent diffusivities and the emerging diffusion profiles of boron and phosphorus. Here, the in‐diffusion of the dopants during diverse doping processes is reproduced by the use of known concentration dependences of the diffusivities in an integrated model. The simulated processes include a BSG drive‐in step in an inert and in a phosphorus‐containing atmosphere. Based on these findings, a PECVD BSG/capping layer structure is developed, which forms three different n⁺⁺−, n⁺− and p⁺−doped regions during one single high temperature process. Such engineered structure can be used to produce back contact solar cells. Copyright © 2016 John Wiley & Sons, Ltd.