CMOS SRAM单粒子翻转效应的解析分析

分析了影响CMOS SRAM单粒子翻转效应的时间因素,指出不能仅根据临界电荷来判断发生单粒子翻转效应与否,必须考虑器件的恢复时间、反馈时间和电荷收集过程.给出了恢复时间和反馈时间的计算方法,提出了器件抗单粒子翻转的加固措施.对电荷收集过程中截止管漏极电位的变化进行了分析,提出了临界电荷新定义,并给出了判断带电粒子入射能否导致器件发生单粒子翻转效应的方法.     

双阱CMOS器件单粒子瞬态效应机理研究

介绍了一种65 nm 双阱CMOS工艺设计的六管SRAM单元的抗辐射性能。通过三维有限元数值模拟的方法,分析了SRAM单元的单粒子瞬态效应在NMOS管中的电荷收集过程和瞬态脉冲电流的组成部分,并提出一种高拟合度的临界电荷计算方案。双阱器件共享电荷诱发的寄生双极放大效应对相邻PMOS管的稳定性有着显著的影响,高线性能量传输提高了器件单粒子翻转的敏感性。电学特性表明,全三维器件数值仿真的方法能够有效评估因内建电势突变产生的瞬态脉冲电流。该方法满足器件仿真对精确度的要求。     

粒子入射条件对28nm SRAM单元单粒子电荷共享效应影响的TCAD仿真研究

利用器件仿真工具TCAD,建立28 nm体硅工艺器件的三维模型,研究了粒子入射条件和器件间距等因素对28 nm体硅工艺器件单粒子效应电荷共享的影响规律。结果表明,粒子LET值增大、入射角度的增大、器件间距的减小和浅槽隔离(STI)深度的减少都会增加相邻器件的电荷收集,增强电荷共享效应,影响器件敏感节点产生的瞬态电流大小;SRAM单元内不同敏感节点的翻转阈值不同,粒子LET值和入射角度的改变会对SRAM单元的单粒子翻转造成影响;LET值和粒子入射位置变化时,多个SRAM单元发生的单粒子多位翻转的位数和位置也会变化。     

PDSOI CMOS SRAM单元临界电荷的确定

PDSOI CMOS SRAM单元的临界电荷(Critical Charge)是判断SRAM单元发生单粒子翻转效应的依据.利用针对1.2μm抗辐照工艺提取的PDSOI MOSFET模型参数,通过HSPICE对SRAM 6T存储单元的临界电荷进行了模拟,指出了电源电压及SOI MOEFET寄生三极管静态增益β对存储单元临界电荷的影响,并提出了在对PDSOI CMOS SRAM进行单粒子辐照实验中,电源电压的最恶劣偏置状态应为电路的最高工作电压.     

GaAsMESFET在抗辐射领域的应用

详细论述了多种辐照源辐射ＧａＡｓＭＥＳＦＥＴ器件和电路产生的ＳＥＵ（单粒子翻转 ）效应，辐照源包括脉冲激光、质子、中子和电子不等。同时还讨论了计算机模拟辐射产生ＳＥＵ的过程和机制。研究表明：１）在低温生长ＧａＡｓ阻支的ＭＥＳＦＥＴ电路，有较强的抗ＳＥＵ能力；２）在ＭＥＳＦＥＴ中，产生ＳＥＵ的原因在于辐射导致了漏极收集电荷的增加，而且，电荷惧增强机制扔三种：ａ）背沟道导通机制，ｂ）双极增益机制；ｃ０     

基于Geant4的三维半导体器件单粒子效应仿真

在空间中,辐射粒子入射半导体器件,会在器件中淀积电荷.这些电荷被器件的敏感区域收集,造成存储器件(如静态随机存储器(SRAM))逻辑状态发生变化,产生单粒子翻转(SEU)效应.蒙特卡洛工具-Geant4能够针对上述物理过程进行计算机数值模拟,可以用于抗辐射器件的性能评估与优化.几何描述标示语言(GDML)能够在Geant4环境下对器件模型进行描述.通过使用GDML建立三维的器件结构模型,并使用Geant4进行不同能量质子入射三维器件模型的仿真.实验结果表明,在三维器件仿真中低能质子要比高能质子更容易引起器件的单粒子翻转效应.     

部分耗尽SOI工艺器件辐射效应的研究

对0.13μm部分耗尽SOI工艺的抗辐射特性进行了研究.首先通过三维仿真研究了单粒子事件中的器件敏感区域,随后通过实验分析了器件的总剂量效应.三维仿真研究了离子入射位置不同时SOI NMOS器件的寄生双极效应和电荷收集现象,结果表明,离子入射在晶体管的体区和漏区时,均可以引起较大水平的电荷收集.对SRAM单元的单粒子翻转效应(SEU)进行了仿真,结果表明,体区和反偏的漏区都是翻转的敏感区域.通过辐照实验分析了器件的总剂量效应,在该工艺下对于隐埋氧化层,关断状态是比传输门状态更劣的辐射偏置条件.     

130 nm NMOS器件的单粒子辐射电荷共享效应

研究了同一p阱内两个130nm NMOS器件在受到重离子辐射后产生的电荷共享效应。使用TCAD仿真构造并校准了130nm NMOS管。研究了在有无p+保护环结构及不同器件间距下,处于截止态的NMOS晶体管之间的电荷共享,给出了电荷共享效应与SET脉冲电流产生的机理。同时分析了NMOS晶体管中的寄生双极管效应对反偏漏体结电荷收集的加剧作用。仿真结果表明,p+保护环可以有效地减小NMOS器件间的电荷共享,加速SET脉冲电流的泄放,证实了p+保护环对器件抗单粒子辐射的有效性,从而给出了该方法在抗单粒子辐射器件版图设计中的可行性。     

一种低功耗低延迟的容忍DNU锁存器设计

随着集成电路器件特征尺寸的进一步减小,锁存器内部节点之间的距离越来越短.由于内部节点间的电荷共享效应,器件在空间辐射环境中频繁发生单粒子翻转(SEU),受影响节点由单节点扩展到双节点.文章提出了一种新型的锁存器加固结构,利用C单元固有的保持属性,实现对单节点翻转(SNU)和双节点翻转(DNU)的完全容忍.HSPICE仿...     

一种基于三联锁结构的单粒子翻转加固锁存器

本文提出了一种基于三联锁结构的单粒子翻转加固锁存器。该锁存器使用保护门和反相器在其内部构建三路反馈,以此获得对发生在任一电路节点上的单粒子效应的自恢复能力,有效抑制由粒子轰击半导体引发的电荷沉积带来的影响。本文在详细分析已报道的三种抗辐射锁存器结构可靠性的基础上,针对其在单粒子效应作用下,或单粒子效应和耦合串扰噪声的共同作用下依然可能发生翻转的问题,指出本文提出的锁存器可通过内部的三联锁结构对上述问题进行有效的消除。所有结论均得到电路级单粒子效应注入仿真结果,以及基于经典串扰模型模拟串扰耦合和单粒子效应共同作用的仿真结果的支持和验证。     

用SOI技术提高CMOS SRAM的抗单粒子翻转能力

提高静态随机存储器（SRAM）的抗单粒子能力是当前电子元器件抗辐射加固领域的研究重点之一。体硅CMOS SRAM不作电路设计加固则难以达到较好抗单粒子能力,作电路设计加固则要在芯片面积和功耗方面做出很大牺牲。为了研究绝缘体上硅（SOI）基SRAM芯片的抗单粒子翻转能力,突破了SOI CMOS加固工艺和128kb SRAM电路设计等关键技术,研制成功国产128kb SOI SRAM芯片。对电路样品的抗单粒子摸底实验表明,其抗单粒子翻转线性传输能量阈值大于61．8MeV／（mg／cm^2）,优于未做加固设计的体硅CMOS SRAM。结论表明,基于SOI技术,仅需进行器件结构和存储单元的适当考虑,即可达到较好的抗单粒子翻转能力。     

Single event upset and total dose radiation effects on rad-hard SRAMs

Radiation hardened 16K and 64K CMOS SRAMs were tested at the Brookhaven SEU Test Facility. No failures of 16K SRAMs were observed at room temperature with any value of the feedback resistors. SEU cross section measured at elevated temperatures was a function of reduced feedback resistance. A difference was observed in critical LET forBr andAu ions. SEU cross section decreased at very high angles of incidence. After initial SEU testing, the 64K SRAM was degraded by proton total dose irradiation. An increase in the SEU cross section as well as imprinting of the memory pattern was observed. Test chips fabricated by the same technology were also submitted to proton radiation. Threshold voltage shift was measured for NMOS transistors with and without inversion bias. An increase in the density of interface states for both NMOS and PMOS transistors was measured by the charge-pumping technique. This research has been supported by the NASA grants NAG-5-929 and NAG-9-333.     

An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs

Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus developed consists of both NMOS and PMOS transistor parameters. Consequently, the model can estimate critical charge variations due to variability of transistor parameters and manufacturing defects, such as resistive contacts and vias. In addition, the model can serve as a tool to optimize the hibernation voltage of low-power SRAMs or the size of MIM capacitor per cell in order to achieve a target soft error robustness. Critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90-nm CMOS process with a maximum discrepancy of less than 5%.      

Novel SEU hardened PD SOI SRAM cell

A novel SEU hardened 10T PD SOI SRAM cell is proposed.By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors,this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU,where the ion affects the single transistor.Through analysis of the upset mechanism of this novel cell,SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references.To achieve this,the new cell adds four transistors and has a 43.4%area overhead and performance penalty.     

一种新式SEU加固PD SOI SRAM单元

本文提出了一种新式SEU加固的10管PD SOI静态存储单元。通过将互锁反相器中的上拉和下拉管分割成两个串联的晶体管,该单元可有效抑制PD SOI晶体管中的寄生BJT和源漏穿通电荷收集效应,这两种电荷收集效应是引起PD SOISRAM翻转的主要原因。通过混合仿真发现,与穿通的浮体6T单元相比,该单元可完全解决粒子入射单个晶体管引起的单粒子翻转。通过分析该新式单元的翻转机制,认为其SEU性能近似与6T SOI SRAM的单粒子多位翻转性能相等。根据参考文献的测试数据,粗略估计该新式单元的SEU性能比普通45nm 6T SOI SRAM单元提升了17倍。由于新增加了四个晶体管,该单元在面积上增加了43.4%的开销,性能方面有所降低。     

High-speed sensing techniques for ultrahigh-speed SRAMs

Two high-speed sensing techniques suitable for ultrahigh-speed SRAMs are proposed. These techniques can reduce a 64-kb SRAM access time to 71~89% of that of conventional high-speed bipolar SRAMs. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAMs for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26~43% of that of conventional cells. A 64-kb SRAM fabricated with one of the sensing techniques using 0.5-μm BiCMOS technology achieved a 1.5-ns access time with a 78-μm² memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAMs, which have been used as cache and control memories of mainframe computers     

温度对SRAM器件单粒子翻转重离子测试的影响

本文基于单粒子效应地面重离子模拟实验,选取体硅SRAM与SOI SRAM两种待测器件,在兰州重离子加速器上（HIRLF）研究了温度对单粒子翻转测试的影响。用12C粒子对体硅SRAM器件的温度实验显示,单粒子翻转截面易受温度的影响。对于SOI SRAM器件,12C粒子测得的单粒子翻转截面随温度升高有显著的增大,但209Bi 粒子测得的单粒子翻转截面却随温度保持恒定。用Monte Carlo的方法分析了温度对单粒子翻转测试的影响规律,发现在单粒子翻转阈值LET附近温度对单粒子翻转截面有大的影响,但是随着单粒子翻转的发生接近于饱和,单粒子翻转截面渐渐的表现出低的温度依赖性。基于该模拟结果,我们对实验数据进行了分析,同时提出了一种准确评估在轨翻转率的合理方法。     

10～20MeV中子引起单粒子翻转的微分析

我们用Monte Carlo方法模拟了10～20MeV中子引起的单粒子翻转。计算了引起电离能量沉积的五种概率。对于一个临界电荷分别为0．05、0．10和0．15pC的16K静态RAM存储器硅片,我们计算了引起单粒子翻转的入射中子平均注量及由(n,α)反应引起的单粒子翻转的概率。给出了三次接近入射中子平均注量的中子引起的单粒子翻转中,在灵敏单元内与电离能量沉积相关的一系列物理量的计算结果。这些结果能够为10～20MeV中子引起的单粒子翻转提供统计的和微观描述的信息。     

Single Event Upset rate determination for 65 nm SRAM bit-cell in LEO radiation environments

The degradation of SRAM bit-cells designed in a 65 nm bulk CMOS technology in a Sun-Synchronous Low Earth Orbit (LEO) ionizing radiation environment is analyzed. We propose an inflight SEU rate estimation approach based on a modeled heavy ion cross section as opposed to the standard experimental characterization. Effects of irradiation with estimated LET spectrum in SRAM bit cell, i.e. the location of sensitive regions, its tendency to cause upset, magnitude and duration of transient current as well as voltage pulses were determined. It was found with SEU map that 65 nm SRAM bit-cell can flip even if high LET particle strikes in close proximity of bit-cell outside the SRAM bit-cell area. The SEU sensitive parameters required to predict SEU rate of on-board target device, i.e., 65 nm SRAM were calculated with typical aluminum spot shielding using fully physical mechanism simulation. In order to characterize the robustness of scaled CMOS devices, state of the art simulation tools such as Visual TCAD/Genius, GSEAT/Visual Particle, runSEU, were utilized whereas LEO radiation environment assessment, upset rate prediction was accomplished with the help of OMERE-TRAD software.     

A 1.5-ns access time, 78-μm2 memory-cell size, 64-kbECL-CMOS SRAM

A 1.5-ns access time, 78-μm² memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers