基于软/硬件协同设计的嵌入式系统的性能测试

本文首先分析了传统的嵌入式系统设计方法及目前流行的软硬件协同设计的方法,指出软硬件协同设计方法是嵌入式领域的一个研究热点,接着分析了传统的测试方式的缺点,然后介绍了AMC公司的CodeTEST嵌入式软件在线分析与测试解决方案,同时也简要介绍了其它几种嵌入式测试工具。     

基于FPGA的软硬件协同仿真加速技术

在系统设计中,硬件复杂电路设计的调试与仿真工作对于设计者来说十分困难。为了降低仿真复杂度,加快仿真速度,本文提出利用FPGA加速的思想,实现软硬件协同加速仿真。经过实验,相对于纯软件仿真,利用软硬件协同加速仿真技术,仿真速度提高近30倍,大大缩短了仿真时间。     

永磁同步电机矢量控制软硬件测试方法

本文以永磁同步电机交流调速开发系统为例,阐述了闭环矢量控制原理与PI参数整定方法,针对整个驱动系统的硬件调试和软件编写测试方法和心得进行详细的讲解,并针对诸多硬件固有的问题提出了利用软件或硬件消除的方法,为科研人员实现产品快速开发提供了有力的保证,对高精度电机控制科研前期工作有着积极的指导意义。     

基于软硬件协同仿真平台的功能仿真测试方法

针对数字信号处理器的不同仿真测试要求,提出了基于软硬件协同仿真平台的功能仿真测试方法。采用软硬件协同仿真测试的方法,提高了被测处理器的仿真测试速度;采用基于指令模型的指令集测试程序,提高了基本指令集的测试覆盖率;采用基于流水控制单元状态机变换路径的测试程序,提高了指令间数据竞争的检测。实验结果表明,指令的覆盖率达到了100％,且DSP处理器代码的覆盖率也达到了满意的程度。     

SOC软硬件协同仿效系统的通讯协议设计

通过对EDA软件仿真器与硬件加速平台的数据传输和信息交换方式的研究,提出并实现了SOC软硬件协同仿效系统的通讯协议。该协议实现了逻辑通道复用技术及端口号寻址的数据传输功能。对基于该协议的SOC软硬件协同仿效系统进行测试试验,结果表明,该协议实现了EDA软件仿真器与硬件加速平台之间数据实时、准确的交换,达到了EDA软件仿真器与硬件加速平台协同仿效的目的。     

A Case Study in Embedded Systems Design: An Engine Control Unit

A number of techniques and software toolsfor embedded system design have been recently proposed. However,the current practice in the designer community is heavily basedon manual techniques and on past experience rather than on arigorous approach to design. To advance the state of the artit is important to address a number of relevant design problemsand solve them to demonstrate the power of the new approaches.We chose an industrial example in automotive electronics to validateour design methodology: an existing commercially available EngineControl Unit. We discuss in detail the specification, the implementationphilosophy, and the architectural trade-off analysis. We analyzethe results obtained with our approach and compare them withthe existing design underlining the advantages offered by a systematicapproach to embedded system design in terms of performance anddesign time.     

利用软件线程集成技术实现嵌入式通信接口

文章阐述了在高温环境下（200℃）利用8位微控制器实现CAN通信网络与异步串行口通信（UART）的链接。软件上采用了一种全新的编译技术-软件线程集成技术，实现任务的并行性。本系统验证了软件线程集成技术在实际工程应用中的可行性。     

移动智能终端软硬件匹配研究

从移动智能终端和PC在软硬件匹配的差异性入手,分析造成目前移动智能终端软硬件匹配问题凸显的根源:即移动智能终端平台间的彼此林立和标准不统一。进而从软硬件匹配的需求入手,分析移动智能终端硬件平台和软件平台在互相匹配方面的技术需求。同时,结合我国移动智能终端整体产业的发展现状和不足进行分析,并从技术、应用和组织三个层面对我国移动智能终端软硬件匹配及一体化创新提出具体的建议。     

嵌入式系统的软硬件协同设计

协同设计改变了传统的设计反复修改系统方案的缺点，通过综合分析系统软硬件功能，最大限度地挖掘系统软硬件之间的并发性，将软硬件开发结合得更紧密，可以大大提高设计效率，使设计出来的系统工作在最佳工作状态。本文将系统地阐述软硬件协同设计技术。     

一种基于改进模拟退火算法的软硬件划分技术

提出一种应用于嵌入式系统软硬件划分的改进模拟退火算法.算法通过使用基于Cauchy分布的扰动模型和Tsallis接收准则来提高模拟退火算法的性能.通过对比经典的模拟退火软硬件划分技术以及实验结果的验证表明,使用改进模拟退火算法能加快划分的收敛,并且找到目标函数的最优值的概率也更大.     

System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search

This paper presents two heuristics for automatic hardware/software partitioning of system level specifications. Partitioning is performed at the granularity of blocks, loops, subprograms, and processes with the objective of performance optimization with a limited hardware and software cost. We define the metric values for partitioning and develop a cost function that guides partitioning towards the desired objective. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria during partitioning. Two heuristics for hardware/software partitioning, formulated as a graph partitioning problem, are presented: one based on simulated annealing and the other on tabu search. Results of extensive experiments, including real-life examples, show the clear superiority of the tabu search based algorithm.     

平台+插件式软件框架模型的研究

对插件式的软件框架模型进行了研究,提出了适用于设备专用软件的"平台+插件"框架模型,描述了该模型的结构、调用过程和实现方式.从有利于设计出高度模块化、可定制、有系列化功能扩展、软件并行开发以及快速集成等方面探讨了该模型的优势.     

嵌入式软硬件系统的可靠性设计

以工程实践中所做的嵌入式软硬件系统可靠性设计为依据,论述了可靠性设计过程中的依据、指标分配以及设计方法。     

Rapid Prototyping of Embedded Hardware/Software Systems

Prototyping of embedded hardware/software systems is important, because it shortens the path from specification to the final product. Prototypes play a major role in decision making, concept and design validation, feature and limit exploration, as well as design verification in every phase of the product development cycle, including product planning, requirement engineering, and product development. This overview discusses the motivation for building prototypes, provides the key areas for research and explains how prototypes can assist in product planning and throughout all steps of the engineering process. Special attention is given to prototyping in the industry to support the design and testing of multimodal and multifunctional embedded systems.     

基于ARM微处理器及嵌入式Linux的串口网桥软硬件设计

介绍ARM7TDMI内核的微处理器S3C4510B在串口网桥设备开发中的应用,以及串口网桥硬件结构的组成和设计,并对基于ARM和uClinux的嵌入式系统软件开发模式进行了探讨.     

基于软硬件协同的机群数据通信机制的研究与实现

针对各种机群互连网络中，由于软硬件协议之间缺乏紧密的配合，而导致网络提供给最终用户的通信效率较低这一问题。提出了基于硬件描述符机制的网卡设计方法和软硬件协同的思想，设计相应的机群通信协议。实现了高性能的机群互连网络，有效提高了机群用户的通信效率及机群互连网络的通信性能     

基于方舟CPU的嵌入式SOC及其软/硬件开发平台

方舟CPU是一款性能优越的国产CPU,GT2000是基于方舟CPU的通用终端系列SOC(片上系统)产品,它的工作频率可以达到400MHz,而功耗仅360mW.本文从嵌入式系统设计与开发的角度,探讨了方舟嵌入式SOC的特性、软件开发工具的使用方法以及基于GT2000的硬件开发平台draco开发板的使用方法.     

A Compositional Framework for Hardware/Software Co-Design

We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derivefrom a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory.     

A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors

Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded processors. Unlike conventional general purpose processors, ASIPs and embedded processors typically run a single application and hence must be optimized extensively for this in order to extract maximum performance. Further, low power and low cost requirements of ASIPs may demand reuse of pipeline stages causing pipelines with complex structural hazards. In such architectures, exploiting higher ILP is a major challenge to the designer.Existing techniques deal with either scheduling hardware pipelines to obtain higher throughput or software pipelining—an instruction scheduling technique for iterative computation—for exploiting greater ILP. We integrate these techniques to co-schedule hardware and software pipelines to achieve greater instruction throughput. In this paper, we develop the underlying theory of Co-Scheduling, called the Modulo-Scheduled Pipeline (or MS-Pipeline) theory. More specifically, we establish the necessary and sufficient condition for achieving the maximum throughput in a given pipeline operating under modulo scheduling. Further, we establish a sufficient condition to achieve a specified throughput, based on which we also develop a methodology for designing the hardware pipelines that achieve such a throughput. Further, we present initial experimental results which help to establish the usefulness of MS-pipeline theory in software pipelining. As the proposed theory helps to analyze and improve the throughput of Modulo-Scheduled Pipelines (MS-pipelines), it is especially useful in designing ASIPs and embedded processors.