Software-programmable digital pre-distortion on new generation FPGAs

In this paper we present a software programmable design flow that facilitates the implementation and integration of efficient digital pre-distortion (DPD) solutions on the leading-edge field programmable gate arrays, combining industry-standard embedded processors and programmable logic fabric into one chip. In addition to software programmability, another key contribution of this design flow is the flexible partitioning of functionality among the hardware and software components, depending on the complexity of the DPD parameter estimation algorithm in use. We have applied processor-specific optimizations to the software implementation and used Vivado high-level synthesis (HLS) tool as the design tool for the programmable logic. Furthermore, we have compared two different techniques for the integration of hardware and software components, where we have chosen the one with better area/latency trade-off. We present a comprehensive study reporting the DPD parameter update times when exploring the partitioning of the functionality among hardware and software. For low-complexity algorithms, we show that a software-only solution is applicable after carrying out the processor-specific software optimizations. For higher-complexity algorithms, we use Vivado HLS to accelerate the time-consuming blocks in the programmable logic, leading to a speed-up factor of up to 7× in the overall algorithm execution time. We present the performance results for two target devices. We also show that our accelerators use only a small portion of the programmable logic fabric on these devices and that a significant reduction of the system’s energy consumption can be obtained by leveraging the FPGA fabric.     

一种面向通信设备的嵌入式软件平台

文章介绍了一种应用于通信设备中的嵌入式软件平台,在给出了嵌入式软件平台的体系架构的基础上,从嵌入式实时操作系统、符合通信行业需求的定制组件和中间件、通信应用软件的集成开发环境3个层面对嵌入式软件平台的关键技术和特点进行了描述,并分析了嵌入式软件平台的经济价值和社会效益.     

The Design and Implementation of Embedded Security CPU Based on Multi-strategy

Control flow monitoring,information flow tracking and memory monitoring are the three main solutions to enhance the security of embedded system at the hardware architecture level.However,most of the current studies about the security of embedded system consider the above solutions in separate dimensions rather than a combined effort.We start from the operation model at the instruction level,and propose a security multi-strategy which combines information flow tracking and memory monitoring by studying the security operating mechanism of embedded system.As a hardware approach this strategy extends the embedded processor architecture with additional security defense control.The experimental results show this multi-strategy is more effective and can detect more malicious attacks than a single solution.The effectiveness of our proposed security multi-strategy has been verified in a Field programmable gate array (FPGA) prototype platform based on a customized Leon3 microprocessor.     

Hardware-software co-design of embedded systems [and prolog]

This paper surveys the design of embedded computer systems, which use software running on programmable computers to implement system functions. Creating an embedded computer system which meets its performance, cost, and design time goals is a hardware-software co-design problem-the design of the hardware and software components influence each other. This paper emphasizes a historical approach to show the relationships between well-understood design problems and the as-yet unsolved problems in co-design. We describe the relationship between hardware and software architecture in the early stages of embedded system design. We describe analysis techniques for hardware and software relevant to the architectural choices required for hardware-software co-design. We also describe design and synthesis techniques for co-design and related problems     

A 64-min single-chip voice recorder/player using embedded 4-b/cellflash memory

A system-on-chip prototype implementing a full integration of a 64-minute digital voice recorder/player and embedding a 4-b/cell multilevel digital flash memory is presented in this paper. A hardwired adaptive-differential pulse-code modulation speech coder/decoder (8 to 40 kb/s) and a microcontroller are integrated into a bus-centric architecture. An 8-Mcell/32-Mb multilevel flash memory is used as an embedded mass storage media and a fully digital on-chip built-in-self-test solution is presented. This speech recording system features a modular architecture allowing full reuse and mix-and-match of its IP building blocks. The architecture of the system and solutions for implementing embedded multilevel flash memories are presented. System operation modes are described showing how the desired message editing functionality is implemented by a mixed hardware/software solution. The chip is 3-V-only and it counts 13 M transistors at 225 mm² area in a 0.5-μm embedded flash technology     

A co-synthesis approach to embedded system design automation

Embedded systems are targeted for specific applications under constraints on relative timing of their actions. For such systems, the use of pre-designed reprogrammable components such as microprocessors provides an effective way to reduce system cost by implementing part of the functionality as a program running on the processor. However, dedicated hardware is often necessary to achieve the requisite timing performance. Analysis of timing constraints is, therefore, key to determination of an efficient hardware-software implementation. In this paper, we present a methodology for embedded system design as a co-synthesis of interacting hardware and software components. We present a decomposition of the co-synthesis problem into sub-problems, that is useful in building a framework for embedded system CAD. In particular, we present operation-level timing constraints and develop the notion of satisfiability of constraints by a given implementation both in the deterministic and probabilistic sense. Constraint satisfiability analysis is then used to define hardware and software portions of functionality. We describe algorithms and techniques used in developing a practical co-synthesis framework, vulcan. Examples are presented to show the utility of our approach.     

基于多软件平台协同工作的FIR滤波器设计

提出了利用多软件平台进行FIR数字滤波器的协同设计,改变了传统的只用硬件电路设计的方法,将整个数字滤波系统的硬件设计趋于软件化,采用Lattice公司的可编程模拟器件ispPAC20和Altera公司的FPGA设计架构整个FIR滤波器实验系统。由于ispPAC20和FPGA器件的高度集成化以及结构的可重构、可编程,使开发人员随时可重复配置满足各种性能要求的滤波器系统,将整个系统变得更小型化、更易于升级维护且更灵活。     

Software radio architecture: a mathematical perspective

As the software radio makes its transition from research to practice, it becomes increasingly important to establish provable properties of the software radio architecture on which product developers and service providers can base technology insertion decisions. Establishing provable properties requires a mathematical perspective on the software radio architecture. This paper contributes to that perspective by critically reviewing the fundamental concept of the software radio, using mathematical models to characterize this rapidly emerging technology in the context of similar technologies like programmable digital radios. The software radio delivers dynamically defined services through programmable processing capacity that has the mathematical structure of the Turing machine. The bounded recursive functions, a subset of the total recursive functions, are shown to be the largest class of Turing-computable functions for which software radios exhibit provable stability in plug-and-play scenarios. Understanding the topological properties of the software radio architecture promotes plug-and-play applications and cost-effective reuse. Analysis of these topological properties yields a layered distributed virtual machine reference model and a set of architecture design principles for the software radio. These criteria may be useful in defining interfaces among hardware, middleware, and higher level software components that are needed for cost-effective software reuse     

FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications

Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/software solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle.     

相控阵雷达中实时雷达控制的设计方法

简要阐述了相控阵雷达中实时雷达控制的特点，介绍了雷达控制的主要功能。提出雷达控制设计过程中的关键技术问题的解决方法，并给出了采用数字信号处理芯片和可编程器件进行设计的软硬件框图，最后略述实时雷达控制系统的应用情况和推广前景。     

Design Methodology for Offloading Software Executions to FPGA

Field programmable gate array (FPGA) is a flexible solution for offloading part of the computations from a processor. In particular, it can be used to accelerate an execution of a computationally heavy part of the software application, e.g., in DSP, where small kernels are repeated often. Since an application code for a processor is a software, a design methodology is needed to convert the code into a hardware implementation, applicable to the FPGA. In this paper, we propose a design method, which uses the Transport Triggered Architecture (TTA) processor template and the TTA-based Co-design Environment toolset to automate the design process. With software as a starting point, we generate a RTL implementation of an application-specific TTA processor together with the hardware/software interfaces required to offload computations from the system main processor. To exemplify how the integration of the customized TTA with a new platform could look like, we describe a process of developing required interfaces from a scratch. Finally, we present how to take advantage of the scalability of the TTA processor to target platform and application-specific requirements.     

Coupling between knowledge-based and algorithmic methods

The integration of knowledge-based techniques with traditional algorithmic software is discussed. Typical problems in power system planning and operation are better solved when the two techniques are combined. Functional aspects of a hybrid problem solving strategy are described and illustrated by two examples from power system operation. Available methods for practical implementation are reviewed. Sample applications from the literature are used to illustrate different approaches to hardware and software integration. Some of these applications have been successfully integrated with existing systems in operational environments. Future energy management systems based on an open architecture are likely to make it easier to integrate knowledge-based systems. Still, software integration issues continue to be a challenge. Particular problems are: automation of complex tasks by intelligent coordination, development of highly flexible software organizational schemes, and methods for easy data exchange between applications based on different software paradigms     

Flexible Circuits and Architectures for Ultralow Power

Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ULP systems across the architecture and circuit levels can meet both the ULP requirements and the performance demands. Specifically, we first present a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points. This system supports operation across the space from maximum performance, when necessary, to minimum energy, when possible. It thus combines the benefits of single-${V}_{rm DD}$ , multi-${V}_{rm DD}$, and dynamic voltage scaling (DVS) while improving on them all. Second, we propose that reconfigurable subthreshold circuits can increase applicability for ULP embedded systems. Since ULP devices conventionally require custom circuit design but the manufacturing volume for many ULP applications is low, a subthreshold field programmable gate array (FPGA) offers a cost-effective custom solution with hardware flexibility that makes it applicable across a wide range of applications. We describe the design of a subthreshold FPGA to support ULP operation and identify key challenges to this effort.      

Mobile agents - enabling technology for active intelligent networkimplementation

The emerging notion of active networks describes the general vision of communication network evolution, where the network nodes become active because they take part in the computation of applications and provision of customized services. In this context mobile agent technology and programmable switches are considered as enabling technologies. This article looks at the impact of mobile agent technology on telecommunication service environments, influenced by the intelligent network (IN) architecture. The authors illustrate how the integration of mobile agent platforms into IN elements, notably into the IN switches, will realize an active IN environment. This enables telecom services implemented through mobile service agents on a per user basis to be instantly deployed at programmable switching nodes, which results in better performance and fault tolerance compared to traditional IN service implementations     

FPGA prototyping of a RISC processor core for embedded applications

Application-specific processors offer an attractive option in the design of embedded systems by providing high performance for a specific application domain. In this work, we describe the use of a reconfigurable processor core based on an RISC architecture as starting point for application-specific processor design. By using a common base instruction set, development cost can be reduced and design space exploration is focused on the application-specific aspects of performance. An important aspect of deploying any new architecture is verification which usually requires lengthy software simulation of a design model. We show how hardware emulation based on programmable logic can be integrated into the hardware/software codesign flow. While previously hardware emulation required massive investment in design effort and special purpose emulators, an emulation approach based on high-density field-programmable gate array (FPGA) devices now makes hardware emulation practical and cost effective for embedded processor designs. To reduce development cost and avoid duplication of design effort, FPGA prototypes and ASIC implementations are derived from a common source: We show how to perform targeted optimizations to fully exploit the capabilities of the target technology while maintaining a common source base     

The rapidly deployable radio network

The rapidly deployable radio network (RDRN) is an architecture and experimental system to develop and evaluate hardware and software components suitable for implementing mobile, rapidly deployable, and adaptive wireless communications systems. The driving application for the RDRN is the need to quickly establish a communications infrastructure following a natural disaster, during a law enforcement activity, or rapid deployment of military force. The RDRN project incorporates digitally controlled antenna beams, programmable radios, adaptive protocols at the link layer, and mobile node management. This paper describes the architecture for the RDRN and a prototype system built to evaluate key system components     

An integrated robot system architecture

This paper describes the architecture of a robot system designed both to work in an integrated manufacturing environment and to support continuing research in programmable automation. Major system components include a controller, robot and sensor hardware, operator's pendant, and system software. A new high-level interactive language, AML, allows the user to combine manipulation, sensing, computational, and data processing functions provided by the system. Important aspects of the system design objectives, major functional components, and the AML language are described, and examples drawn from an actual production application are used to illustrate the interrelationship of the topics discussed.     

A family of user-programmable peripherals with a functional unitarchitecture

A family of user-programmable peripherals, utilizing an integration strategy based on a programmable system device (PSD) concept, is described. Specifically, PSD is an efficient and highly configurable integration of high-density memory and LSI level logic blocks. The configurability is derived by providing programmable logic and programmable interconnect. PSDX is the first PSD family of programmable microcontroller peripherals; it integrates 256 kb to 1 Mb of EPROM, 16 kb of SRAM, a 28-input by 42-product term programmable logic device (PLD), and flexible I/O ports. This family is primarily targeted for embedded microcontroller applications. Using one PSD device it is possible to replace all the core peripherals in the system and, as a result, achieve a reduction in components, power dissipation, and overall system cost. The flexible architecture is achieved by providing 46 configuration options, which allows the PSD to interface with virtually any 8- or 16-b microcontroller. The integration is made possible by developing a special configurability and testability scheme. These parts are realized on a 1.2-μm CMOS EPROM process