Estimating the noise mitigation effect of local decoupling in printed circuit boards

Local decoupling, i.e., placing decoupling capacitors sufficiently close to device power/ground pins in order to decrease the impedance of power bus at frequencies higher than the series resonant frequency, has been studied using a modeling approach, a hybrid lumped/distributed circuit model established and an expression to quantify the benefits of power bits noise mitigation due to local decoupling developed. In this work, a test board with a local decoupling capacitor was studied and the noise mitigation effect due to the capacitor placed adjacent to an input test port was measured. Closed-form expressions for self and mutual inductances of vias are developed, so that the noise mitigation effect can then be estimated using the previously developed expression. The difference between the estimates and measurements is approximately 1 dB, which demonstrates the application of these closed-form expressions in the PCB power bus designs. Shared-via decoupling, capacitors sharing vias with device power/ground pins, is also modeled as an extreme case of local decoupling.     

DC power-bus design using FDTD modeling with dispersive media andsurface mount technology components

DC power-bus modeling in high-speed digital design using the finite-difference time-domain (FDTD) method is demonstrated herein. The dispersive character of the dielectric layers used in printed circuit board substrates is taken into account in this study. In particular, FR-4 is considered. The complex permittivity of the dielectric is approximated by a Debye model. A wide-band frequency response (100 MHz-5 GHz) is obtained through a single FDTD simulation. Good agreement is achieved between the modeled and measured results for a typical dc power-bus structure with multiple surface mount technology (SMT) decoupling capacitors placed on the printed circuit board (PCB). The FDTD method is then applied to investigate some general approaches of power-bus noise decoupling     

Lumped-circuit model extraction for vias in multilayer substrates

Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted in a systematic manner using this approach. A closed-form expression for via self inductance is further derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expression can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power-bus impedance as well as effective frequency range of decoupling capacitors.     

高速PCB电源完整性研究

一块成功的高速印刷电路板(PCB),需要做到信号完整性和电源完整性,首先必须降低地弹.为了滤除地弹骚扰,推荐在电源/地平面对上,安放去耦电容。     

Modeling and simulation of integrated capacitors for high frequencychip power decoupling

Power and ground decoupling is typically accomplished using a hierarchy of discrete capacitors spread throughout the power distribution network. Many of the limitations of discrete decoupling capacitors can be overcome with integrated capacitors. A modeling approach for integrated capacitors based on the partial-element-equivalent-circuit (PEEC) formulation is presented. This approach has been applied to 3M C-ply, a flexible planar integrated capacitor technology that can be laminated into multilayer substrates, such as printed wiring boards. The decoupling capability of 3M C-Ply technology for chip power distribution has been compared with conventional surface-mount technology (SMT)     

An efficient path-based equivalent circuit model for design, synthesis, and optimization of power distribution networks in multilayer printed circuit boards

In high-speed printed circuit boards, the decoupling capacitors are commonly used to mitigate the power-bus noise that causes many signal integrity problems. It is very important to determine their proper locations and values so that the power distribution network should have low impedance over a wide range of frequencies, which demands a precise power-bus model considering the decoupling capacitors. However, conventional power-bus models suffer from various problems, i.e., the numerical analyzes require huge computation while the lumped circuit models show poor accuracy. In this paper, a novel power-bus model has been proposed, which simplifies the n-port Z-parameters of a power-bus plane to a lumped T-network circuit model. It exploits the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors, while the conventional lumped models assume that all decoupling capacitors are connected in parallel, independently with each other. It also models the equivalent electrical parameters of the board parasitic precisely, while the conventional lumped models employ only the inter-plane capacitance of the power-ground planes. Although it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. Consequently, the proposed model enables a quick and accurate optimization of power distribution networks in the frequency domain by determining the locations and values of the decoupling capacitors.     

Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).     

Modeling DC power-bus structures with vertical discontinuitiesusing a circuit extraction approach based on a mixed-potential integralequation

The DC power-bus is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation is presented herein to model arbitrary multilayer power-bus structures with vertical discontinuities that include decoupling capacitor interconnects. Green's functions in a stratified medium are used and the problem is formulated using a mixed-potential integral equation approach. The final matrix equation is not solved, rather, an equivalent circuit model is extracted from the first-principles formulation. Agreement between modeling and measurements is good, and the utility of the approach is demonstrated for DC power-bus design     

Effective Radii of On-Chip Decoupling Capacitors

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard cell circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A design methodology for placing on-chip decoupling capacitors is presented in this paper. A maximum effective radius is shown to exist for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is ineffective. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop seen at the current load is caused either by the first droop (determined by the rise time) or by the second droop (determined by the transition time). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. In order to provide the required charge drawn by the load, the decoupling capacitor has to be charged before the next switching cycle. For an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.     

DC power-bus modeling and design with a mixed-potentialintegral-equation formulation and circuit extraction

The application of a circuit extraction approach based on a mixed-potential integral equation formulation (CEMPIE) for DC power-bus modeling in high-speed digital designs is detailed. Agreement with measurements demonstrates the effectiveness of the approach. Dielectric losses are included into the calculation of the Green's functions, and thus, incorporated into the rigorous first principles formulation. A SPICE model is then extracted from the discretized integral equation. A quasistatic approximation is used for the Green's functions to keep the extracted circuit elements frequency independent. Previous work has established a necessary meshing criterion in order to ensure accuracy for a given substrate thickness and dielectric constant to a desired frequency. Several power-bus design issues, such as surface mount decoupling and power-plane segmentation, were investigated using the modeling approach. The results and discussions illustrate the application of the method to DC power-bus design for printed circuit and multi-chip module substrates     

Modeling and analysis of power distribution networks for Gigabit applications

As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PGBA) packages on a PCB. In this paper, a hybrid method has been applied for analysis, which consists of the transmission matrix method (TMM) in the frequency domain and macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.     

Study of the ground bounce caused by power plane resonances

We describe Delta-I noise caused by power plane resonances in multilayer boards. First, we study the effect of power plane resonances on the ground bounce of the system by performing finite-difference time-domain (FDTD) simulations. We simulate the voltage fluctuations at one point of the printed circuit board (PCB) due to a current surge between the power planes in a different point. Next, two methods to prevent this ground bounce effect are investigated. The first method consists of adding lumped capacitances to the design. The effect of one large capacitor is compared to the effect of adding a “wall” of smaller capacitors. A second approach is to isolate the chips by etching a slot around the sensitive integrated circuits (ICs) and connecting both sides by a small inductor. Both methods provide excellent protection against power plane resonances     

Quantifying the effect of local interconnects on on-chip power distribution

Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.     

FDTD modeling incorporating a two-port network for I/O line EMIfiltering design

Electromagnetic interference (EMI) filters are often utilized on I/O lines to reduce high-frequency noise from being conducted off the printed circuit board (PCB) and causing EMI problems. The filtering performance is often compromised at high frequencies due to parasitics associated with the filter itself, or the PCB layout and interconnects. Finite difference time domain (FDTD) modeling can be used to quantify the effect of PCB layout and interconnects, as well as filter type, on the EMI performance of I/O line filtering. FDTD modeling of a T-type and π-type filter consisting of surface-mount ferrites and capacitors is considered herein. The FDTD method is applied to model PCB layout and interconnect features, as well as the lumped element components, including the nonlinear characteristics of ferrite surface-mount parts. The EMI filters with ferrites; are included in the modeling by incorporating the time-domain Y-parameters of the two-port network into the FDTD time-marching equations. Good agreement between the FDTD modeling and S-parameter measurements supports the new FDTD algorithm for incorporating two-port networks     

GA-optimized decoupling capacitors damping the rectangular power-bus' cavity-mode resonances

The genetic algorithm (GA) is suggested to find the decoupling capacitors for suppressing the cavity-mode resonances in the printed circuit board power-bus structure. The optimal positions and circuital values of decoupling capacitors are efficiently determined to selectively mitigate specific resonance peaks. The optimization of the damping is validated with the measurement and develops to multiresonance modes' damping.     

高精度电容器建模设计

针对电源分配网络设计不当使电源噪声过大的问题,提出了基于[CX2]S[CX]参数测量及矢量拟合的电容器Spice建模方法,并与传统的蒙特卡罗法建模进行比较,证明此电容器建模方法建模精度高,基于得到的电容器模型提出了最大违背点去耦选电容算法,解决了人工选择去耦电容器方案时反复设计的问题。     

Improvements in Noise Suppression for I/O Circuits Using Embedded Planar Capacitors

The performance of embedded planar capacitors in noise suppression of input/output (I/O) circuits and improvements in board impedance profile have been investigated in this paper. Simultaneous switching noise (SSN) is a critical issue in today's systems and this paper shows performance improvements by introducing thin planar embedded capacitors in the board stack up. Measurement and modeling results by including the effects of transmission lines and the power ground plane pairs in the board stack up in the gigahertz range quantify the performance of the embedded capacitors.     

Electromagnetic Design Techniques for Liquid Crystal Display Driver ICs

A simple method of verifying electromagnetic interference (EMI) reduction effects for liquid crystal display (LCD) driver integrated circuits (ICs) is proposed. In this paper, we discuss correlations between radiated emissions and high-frequency currents of power system at three different levels: print circuit board (PCB) level, chip level, and functional circuit level. The EMI design points for LCD driver ICs are presented too. Simulated and measured results prove that our EMI design effectively reduces LCD EMI noise.     

On-chip decoupling capacitor optimization using architectural level prediction

Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.     

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs

Control of on-chip power supply noise has become a major challenge for continuous scaling of CMOS technology. Conventional passive decoupling capacitors (decaps) exhibit significant area and leakage penalties. To improve the efficiency of power supply regulation, this paper proposes a distributed active decap circuit for use in digital integrated circuits (ICs). The proposed design uses an operational amplifier to boost the performance of conventional decaps. Simulations proved its enhanced decoupling effect in comparison with passive decaps. The proposed active decap also shows advantages in providing additional damping to the on-chip resonant noise. To verify the performance from the proposed circuit, a 0.18-$mu$ m test chip with on-chip noise generators and sensors has been fabricated. Measurements show a 4-11$times$ boost in decap value over conventional passive decaps for frequencies up to 1 GHz with a total area saving of 40%. Local supply noise distribution and decap gating capability were also examined from the test chip.