离子束刻蚀HgCdTe环孔pn结I-V、RD-V特性的研究（下）

本文推导了一种可简便、准确、直观计算和分析pn结I-V特性的公式和方法,并应用该方法对两类典型HgCdTe环孔pn结的I-V、RD—V特性进行了计算和拟合;得到了表面欧姆（反型沟道）漏电导、二极管理想因子n随电压的分布等反映二极管结特性的重要参数。计算结果表明,对于长波HgCdTe光伏器件而言,表面漏电流在整个暗电流中所占的比重相当大,表面漏电流严重地制约着器件性能。HgCdTe材料的晶体缺陷会使二极管的理想因子n增大,从而使产生一复合电流及陷阱辅助隧穿电流增加。     

离子束刻蚀HgCdTe环孔pn结Ⅰ—Ⅴ、R_D—V特性的研究(下)

本文推导了一种可简便、准确、直观计算和分析pn结Ⅰ-Ⅴ特性的公式和方法,并应用该方法对两类典型HgCdTe环孔pn结的Ⅰ-Ⅴ、R_D-V特性进行了计算和拟合;得到了表面欧姆(反型沟道)漏电导、二极管理想因子n随电压的分布等反映二极管结特性的重要参数。计算结果表明,对于长波HgCdTe光伏器件而言,表面漏电流在整个暗电流中所占的比重相当大,表面漏电流严重地制约着器件性能。HgCdTe材料的晶体缺陷会使二极管的理想因子n增大,从而使产生-复合电流及陷阱辅助隧穿电流增加。     

离子束刻蚀HgCdTe环孔pn结I–V、RD–V特性的研究（下）

本文推导了一种可简便、准确、直观计算和分析pn结I–V特性的公式和方法,并应 用该方法对两类典型HgCdTe环孔pn结的I–V、RD–V特性进行了计算和拟合;得到了表面欧姆(反型沟道)漏 电导、二极管理想因子n随电压的分布等反映二极管结特性的重要参数。计算结果表明,对于长波HgCdTe 光伏器件而言,表面漏电流在整个暗电流中所占的比重相当大,表面漏电流严重地制约着器件性能。HgCdTe 材料的晶体缺陷会使二极管的理想因子n增大,从而使产生–复合电流及陷阱辅助隧穿电流增加。     

离子束刻蚀HgCdTe环孔pn结Ⅰ-Ⅴ、RD-Ⅴ特性的研究(下)

本文推导了一种可简便,准确、直观计算和分析pn结Ⅰ-Ⅴ特性的公式和方法,并应用该方法对两类典型HgCdTe环孔pn结的Ⅰ-Ⅴ、RD-Ⅴ特性进行了计算和拟合;得到了表面欧姆(反型沟道)漏电导、二极管理想因子n随电压的分布等反映二极管结特性的重要参数.计算结果表明,对于长波HgCdTe光伏器件而言,表面漏电流在整个暗电流中所占的比重相当大,表面漏电流严重地制约着器件性能.HgCdTe材料的晶体缺陷会使二极管的理想因子n增大,从而使产生-复合电流及陷阱辅助隧穿电流增加.     

离子束刻蚀HgCdTe环孔pn结Ⅰ-Ⅴ、R_D-V特性的研究(上)

本文推导了一种可简便、准确、直观计算和分析pn结Ⅰ-Ⅴ特性的公式和方法,并应用该方法对两类典型HgCdTe环孔pn结的Ⅰ-Ⅴ、R_D-V特性进行了计算和拟合;得到了表面欧姆(反型沟道)漏电导、二极管理想因子n随电压的分布等反映二极管结特性的重要参数。计算结果表明,对于长波HgCdTe光伏器件而言,表面漏电流在整个暗电流中所占的比重相当大,表面漏电流严重地制约着器件性能。HgCdTe材料的晶体缺陷会使二极管的理想因子n增大,从而使产生-复合电流及陷阱辅助隧穿电流增加。     

Hg1—xCdxTeN^＋—P栅控二极管表面沟道漏电的理论和实验研究

制备了HgCdTe离子注入N~+-P栅控二极管.测量结果表明,由P区一侧表面强反型引起的表面沟道漏电严重限制着器件性能,对这种漏电机制进行了详细的理论分析.在考虑了窄禁带HgCdTe的特殊性质后,计算了表面沟道电流决定的P-N结正、反向I-V特性和R_0A的温度特性,以及它们与表面状态的关系.理论与实验定性相符.     

HgCdTe器件中pn结结区扩展的表征方法

报道了液氮温度下激光束诱导电流(LBIC)和I-V测试两种在HgCdTe器件中pn结结区扩展的表征方法.通过LBIC和I-V测试,发现了p型HgCdTe材料中由B+离子注入成结和干法刻蚀成结对材料造成的损伤使得有效结区范围大于注入和刻蚀面积,并获得n区横向扩展.同时,通过对比,相互印证两种方法得到的测试结果一致.     

砷掺HgCdTe长波红外光电二极管阵列的制备与性能

采用砷(As)掺杂HgCdTe材料研制了响应截止波长为12.5 μm,规格为256×1的长波红外光电二极管阵列.实验设计了一种新的pn结测量方法,测量发现砷掺长波HgCdTe材料离子注入形成pn结深度在3.6～5.3 μm之间,而其最大横向尺寸大约是设计尺寸的1.3倍.实验采用一种改进的表面处理工艺制备了砷掺HgCdTe长波红外光电二极管阵列,获得了良好的电学性能,该工艺与常规表面处理工艺相比可以使器件峰值阻抗提高2个量级,而-0.5v偏压下的动态电阻可提高约30倍.研究认为,器件性能提高的原因是由于改进工艺可以有效抑制器件表面漏电流.     

甚长波碲镉汞光伏探测器伏安特性分析

分析了注入同质结N-on-P和液相外延异质结P-on-N碲镉汞甚长波红外探测器在不同工作温度下的I-V特性,并对R-V特性进行了仿真计算,对比了扩散电流、产生-复合电流、表面漏电流、带间隧穿电流和缺陷辅助隧穿电流等暗电流对两种器件R-V特性的不同影响。     

CdTe/ZnS复合钝化层对长波碲镉汞器件性能的影响研究

采用CdTe/ZnS复合钝化技术对长波HgCdTe薄膜进行表面钝化,并对钝化膜生长工艺进行了改进。采用不同钝化工艺分别制备了MIS器件和二极管器件,并进行了SEM、C-V和I-V表征分析,研究了HgCdTe/钝化层之间的界面特性及其对器件性能的影响。结果表明,钝化工艺改进后所生长的CdTe薄膜更为致密且无大的孔洞,CdTe/HgCdTe界面晶格结构有序度获得改善;采用改进的钝化工艺制备的MIS器件C-V测试曲线呈现高频特性,界面固定电荷面密度从改进前的1.671011 cm-2下降至5.691010 cm-2;采用常规钝化工艺制备的二极管器件在较高反向偏压下出现较大的表面沟道漏电流,新工艺制备的器件表面漏电现象获得了有效抑制。     

Surface leakage current analysis of ion implanted ZnS-passivated n-on-p HgCdTe diodes in weak inversion

Effects of fixed charge on R₀A value of ZnS-passivated x=0.3 HgCdTe n-on-p diode are explained as a shunt resistance that affects current-voltage (I-V) and dynamic resistance-voltage (Rd-V) characteristics. The fixed charge of 1×10¹¹/cm² to 2 × 10¹¹/cm² which is usually obtained with ZnS passivation makes the surface weakly inverted and reduces HgCdTe diode R₀A value owing to the short generation lifetime of HgCdTe substrate. The gate-controlled diode and specially fabricated diode are used to explain the surface leakage current in the weak inversion and charge sheet model is used to explain the characteristics. It is found that the surface leakage current by the inverted channel in the weak inversion can reduce R₀A more than other currents such as the generation current and tunneling current which are usually used to explain the surface leakage current of HgCdTe diode.     

HgCdTe long-wavelength infrared photovoltaic detectors fabricated using plasma-induced junction formation technology

A long-wavelength infrared (LWIR) HgCdTe photodiode fabrication process has been developed based on reactive ion etching (RIE) plasma-induced p-to-n type conversion for junction formation. The process has been successfully applied to produce devices using both vacancy-doped and gold-doped liquid phase epitaxy (LPE)-grown p-type HgCdTe material with a cut-off wavelength of 10 μm at 77 K. The fabrication procedure is outlined and results are presented on completed devices that indicate the effect of variations in processing parameters. The fabricated devices have been characterized by measurements of the diode dark I-V characteristic over the temperature range 20–200 K, as well as by spectral responsivity measurements. Analysis of the device I-V data, variable area data, and modeling of diode dark current mechanisms indicates that gold-doped material results in higher performing devices compared to vacancy-doped material. Device performance is found to be strongly affected by trap-assisted tunneling currents and surface leakage currents at zero bias. Nonoptimum surface passivation is likely to be the major factor limiting performance at this early stage of device technology development.     

基于栅控二极管研究碲镉汞器件表面效应

采用不同工艺生长了CdTe/ZnS复合钝化层,制备了相应的长波HgCdTe栅控二极管器件并进行了不同条件下I-V测试分析.结果表明,标准工艺制备的器件界面存在较高面密度极性为正的固定电荷,在较高的反偏下形成较大的表面沟道漏电流,对器件性能具有重要的影响.通过钝化膜生长工艺的改进有效减小了器件界面固定电荷面密度,使HgCdTe表面从弱反型状态逐渐向平带状态转变,表面效应得到有效抑制,器件反向特性获得显著改善.此外,基于最优的工艺条件制备的器件界面态陷阱数量得到大幅降低,器件稳定性增强;同时器件R_0A随栅压未发生明显地变化.     

A model for dark current and multiplication in HgCdTe avalanche photodiodes

In this paper we report the calculated results of the dark current and multiplication factor in MBE grown HgCdTe avalanche photodiodes with separate absorption and multiplication (SAM-APD). The device architecture used for this analysis comprises the following layers: p⁺ contact, p junction, n⁻ multiplication, n charge sheet, n⁻ absorber, and n⁺ contact. Various leakage current mechanisms are considered and the generation-recombination term is found to be the dominant one for this device structure. However, experimental reverse bias I-V characteristics reported earlier by T. de Lyon et al. shows a large deviation from ideality, which can not be explained in terms of bulk leakage current mechanism. To explain the large difference between experimental and theoretical data we consider that the dominant generation-recombination current is multiplied through impact ionization process. To validate this assumption, multiplication is calculated as a function of reverse bias. Electric field profile is obtained and the multiplication is computed using the ionization coefficients and avalanche gain equations. Breakdown voltage is found to be 85 V for room temperature operation in agreement with available data in the literature. The theoretical I-V curves considering multiplication are compared with the experimental ones and a close agreement is found which validate this model.     

多晶PIN二极管及二极管串作良好工艺兼容并可移植ESD保护器件的研究

作为静电保护保护器件,多晶PIN二极管具有良好工艺兼容性及可移植的优点。文章制作并展示了多晶PIN二极管的反向击穿电压、漏电流及电容特性,同时通过正向及反向传输线脉冲电流电压特性评估了其静电保护能力。另外为了经一部降低电容并控制反向崩溃及正向开启电压对多晶PIN二极管串进行了研究。最后对器件特性进行了分析讨论,阐明了器件参数对性能的影响。     

Characterization of shallow silicided junctions for sub-quartermicron ULSI technology. Extraction of silicidation induced Schottkycontact area

The current-voltage (I-V) characteristics of shallow silicided p ⁺-n and n⁺-p junctions are presented. In the former the diode behavior was same as in nonsilicided junction, while drastic change in diode I-V was observed in the latter. The formation of Schottky contact was conclusively shown to be the root cause of the modified I-V behavior of n⁺-p junction in the forward bias region. Poole-Frenkel barrier lowering predominantly influenced the reverse leakage current, masking thereby the effect of Schottky contact. The leakage current in n⁺-p diodes was higher than in nonsilicided diodes by two orders of magnitude and this is consistent with the formation of Schottky contact via titanium or titanium-silicide penetrating into the p-substrate and generating trap sites. There is no increase in the leakage current and no formation of Schottky contact in case of the p⁺-n junction. The Schottky contact amounting to less than 0.01% of the total junction area and not amenable for SEM or TEM observation was extracted for the first time by simultaneous characterization of forward and reverse characteristics of silicided n ⁺-p diode     

Dark currents in long wavelength infrared HgCdTe gated photodiodes

The fabrication of HgCdTe photodiodes using plasma-induced p-to-n type conversion for junction formation shows promise in improving array uniformity and device yields in comparison to more traditional fabrication technologies. Previously, characterization and analysis of the diode current-voltage (I–V) characteristics of fabricated devices have given indications that surface-leakage current mechanisms are limiting device performance. To further investigate the effectiveness of the surface passivation employed in the fabrication process, gated-diode structures have been fabricated. The gated-diode structure enables the semiconductor surface potential to be varied, thus allowing the characteristics of surface-leakage currents and their effect on device performance to be evaluated. The long wavelength infrared (LWIR) HgCdTe gated photodiodes used in this study have been characterized using I–V measurements for variable gate-bias voltage and variable temperature. Analysis of the experimental results indicates that plasma-induced type conversion produces an n (lightly doped)-on-p junction that is highly susceptible to a trapped positive charge in the passivation layer, which results in increased surface-tunneling currents. Modeling of the various dark-current mechanisms is used to show the effect on dark-current generation of the surface band bending induced by variations in surface potential. In addition, temperature-dependent I–V measurements and analysis have also been conducted.     

LWIR HgCdTe on Si detector performance and analysis

We have fabricated a series of 256 pixel×256 pixel, 40 μm pitch LWIR focal plane arrays (FPAs) with HgCdTe grown on (211) silicon substrates using MBE grown CdTe and CdSeTe buffer layers. The detector arrays were fabricated using Rockwell Scientific’s double layer planar heterostructure (DLPH) diode architecture. The 78 K detector and focal plane array (FPA) performance are discussed in terms of quantum efficiency (QE), diode dark current and dark current operability. The FPA dark current and the tail in the FPA dark current operability histograms are discussed in terms of the HgCdTe epitaxial layer defect density and the dislocation density of the individual diode junctions. Individual diode zero bias impedance and reverse bias current-voltage (I-V) characteristics vs. temperature are discussed in terms of the dislocation density of the epitaxial layer, and the misfit stress in the epitaxial multilayer structure, and the thermal expansion mismatch in the composite substrate. The fundamental FPA performance limitations and possible FPA performance improvements are discussed in terms of basic device physics and material properties.