可模拟仪表放大器的放大器和电流源

经典的三运放或二运放仪表放大器电路都是放大内含高共模噪声的小振幅差动信号的标准方法.在有些应用场合,信号源随高串行输出阻抗而波动,因而需要使用高输入阻抗放大器.     

双运放仪表放大器

讨论了仪表放大器在传感器信号调理中的作用,介绍了一种双运放仪表放大器的组成结构、性能特点并给出了设计实例.     

利用精密仪表放大器实现负压电流检测

监测正电源的电流时，通常使用高边检流放大器。然而，对于ISDN、电信电源，通常需要一个工作在负电源的检流放大器。本文介绍了一种采用MAX4460单电源仪表放大器设计负压检流放大器的方法。     

智能化传感器中应用仪表放大器的电路设计

在智能化传感器系统中广泛采用仪表放大器构成信号的放大处理电路。放大差分信号的仪表放大器在实际应用中,要考虑输入共模电压范围、增益的选择、滤波、共模频率、输入电流回路设计等问题,以及选择信号的输入方式。针对这些问题,本文进行了较为详尽的讨论。     

用两只仪表放大器制作精密的电压-电流源

很多设计都需要精密的压控电流源．尤其是在可变负载情况下。通常的方法是使用几支运放和一些无源元件．但由于元器件特性不理想而会有固有的误差，如有限的开环增益、共模抑制、偏置电流和补偿电压。采用运算放大器的设计可能需要使用设定增益精密电阻．以及保持稳定的额外电容。另外．有些电路设计提供的电流并不与输入电压直接成正比。例如．图1中的电压一电流转换器就要求集电极电流约等于射级电流．并且只提供一个方向的电流。     

数字输出三轴加速计

LIS3DH的工作电流消耗最低为2μA,这款3mm×3mm×1mm的加速传感器最适合运动感应功能、空间和功耗均受限的应用设计。在±2g／±4g／±8g／±16g全量程范围内,其可提供非常精确的测量数据输出,在额定温度和长时间工作下,仍能保持卓越的稳定性。     

仪表放大器对热敏电阻风速传感器的误差改进

热敏电阻风速传感器的工作原理是测量风速,热敏电阻值和输出电压间关系,导致热敏电阻风速传感器的测量误差偏大.热敏电阻风速传感器的精度主要依赖热敏电阻选型和桥电路及相关运放电路的改进,实验表明,采用仪表放大器AD627可以比运算放大器获得更高的输出电压精度,减小热敏电阻风速传感器在电路部分的误差.     

一种输入输出轨到轨的电流模式仪表放大器设计

本文提出了一种基于标准CMOS工艺的电流模式仪表放大器.该放大器内部运放采用斩波调制技术去除低频1/f噪声和失调,并采用正、负电荷泵,使系统具有轨到轨的输入能力.芯片使用TSMC 0.25μm CMOS混合信号工艺模型设计并流片.测试结果表明,使用60kHz的斩波频率,系统增益为40dB时,具有100dB的共模抑制比和...     

Uncoupling micromachined-based piezoelectric accelerometer performance from a sensor structure transfer function

A smart structure technology for autonomous gain and phase tailoring was adapted to develop a new accelerometer that possesses both an excellent low-frequency response and a high operational bandwidth. The freedom associated with the uncoupling of the gain and phase tailoring to an accelerometer-based structure transfer function can be shown to vastly expand the performance area of traditional accelerometers. We used free-fall detection to demonstrate this newly found capability with its wide applicability to portable devices and which is perceived as extremely difficult to pursue for magnetic disk drives. A micromachined accelerometer was developed to demonstrate the expanded applicability of this innovative concept that integrates smart structure technology to accelerometer design. Both theoretical derivations and experimental verification of this new class of accelerometers are detailed in this paper.     

Current-mode divide-by-two circuit

A current-mode divide-by-two circuit is presented which does not rely on well matched components and a high gain opamp. The circuit can be employee as a reference-generating circuit of an algorithmic current-mode A/D convertor.<>     

Current-mode algorithmic analog-to-digital converters

A current-mode technique for the design of algorithmic analog-to-digital converters (ADCs) is presented. The current-mode technique allows the necessary voltage swing for a given dynamic range to be reduced while at the same time eliminating the need for large capacitors on which to store the signal. Consequently, the resulting ADCs can be made very small and yet still capable of providing high sampling rates. The advantages and disadvantages of different current mirror structures for use in ADCs are discussed. Experimental results for ADCs fabricated using a 3-μm CMOS process are reported, including an 8-b ADC which displayed a sampling rate of 500 kHz and a total circuit area of under 0.75 mm²     

Current-mode KHN-equivalent biquad using CDBAs

A new Kerwin-Huelsman-Newcomb (KHN)-equivalent biquad, operating in the current mode (CM), is proposed. The proposed circuit is derived from the adjoint graph of the signal flow graph corresponding to the classical KHN circuit. The derived circuit is a CM universal filter, which offers all the main advantages of CM circuits as well as those of the classical KHN circuit. The proposed circuit employs three current differencing buffered amplifiers (CDBAs) as active elements. In addition to the three basic filter responses, it also allows the realisation of the notch and allpass responses without requiring any element matching conditions     

Current-mode CMOS quaternary multiplier circuit

A new current-mode CMOS quaternary multiplier circuit is presented. This circuit accepts two 4-valued input currents and a 3-valued CARRY input current and generates a 4-valued SUM output current and a 3-valued CARRY output current. It uses 49 MOS transistors and generates the product in ~10 μs, worst case, in simulations     

Current-mode differential wave active filters

A technique for obtaining differential active filters suitable for integrated circuit implementation is presented. These filters, based on current-mode differential-wave active blocks, can operate at high frequencies. The cutoff frequency can by tuned by the bias current. The proposed filter topologies are modular and very flexible for both the electronic and the physical design. Simulation results of a third-order elliptic filter, designed in a 0.35-/spl mu/m CMOS technology, are presented.     

一种新型的电流模式曲率补偿带隙基准源

提出了一种新型的低压带隙基准源,与传统的带隙基准不同,该电路引入了第三个电流,以消除双极型晶体管射基电压的温度非线性项,从而实现曲率补偿。采用0．18μmCMOS工艺进行设计验证,HSpice仿真结果表明,室温下的输出电压为623mV,-55～＋125℃范围内的温度系数为4．2ppm／℃,1．0～2．1V之间的电源调整率为0．9mV／V。     

Current-mode biquad using OTAs and CF

A novel current-mode biquad using operational transconductance amplifiers (OTAs) and current follower (CF) is presented. The circuit can realise lowpass, bandpass, highpass, band-stop and all-pass transfer functions without any circuit matching conditions. The circuit parameters can also be tuned independently by the transconductance gains of the OTAs. The proposed biquad enjoys very low sensitivities with respect to the circuit elements.     

基于改进型CCII的电流模式多功能二阶滤波器

本文给出了一种结构简单性能优良的改进型电流传送器，并提出了由该电流传送器实现的电流模式多功能双二阶滤波器。该滤波器由三个ＣＣＩ±和五个无源元件构成，可以实现二阶低通、高通、带通带阻和全通滤波功能，且可以多端输出，电路中电阻电容全部接地，适于全集成。中心频率和品质因数的无源灵敏度很低，面向实际电路完成ＭＯＳ管级的ＰＳＰＩＣＥ仿真，结果表明所提出的电路方案是可行的。     

Current-mode fully-programmable piece-wise-linear block forneuro-fuzzy applications

A new method to implement an arbitrary piece-wise-linear characteristic in current mode is presented. Each of the breaking points and each slope is separately controllable. As an example a block that implements an N-shaped piece-wise-linearity has been designed. The N-shaped block operates in the subthreshold region and uses only ten transistors. These characteristics make it especially suitable for large arrays of neuro-fuzzy systems where the number of transistors and power consumption per cell is an important concern. A prototype of this block has been fabricated in a 0.35 μm CMOS technology. The functionality and programmability of this circuit has been verified through experimental results