基于一种交织码的多位翻转容错技术研究

随着技术的发展和核心电压的降低,存储器更易受瞬时错误（软错误）影响,成为影响航天器件可靠性的主要原因。错误检测与纠正（EDAC）码（也称错误纠正码）常用来对SRAM型存储器中的瞬时错误进行纠正,由单个高能粒子引起的多位翻转错误（SEMU）是普通纠一检二（SEC-DED）编码所无法处理的。提出了一种交织度为2的(26,16)交织码,该码由两个能纠正一位随机错误、二位突发错误的(13,8)系统码组成,(26,16)交织码能够纠正单个码字中小于二位的随机错误和小于四位突发错误（DEC-QAEC）。通过理论分析和硬件平台实验表明,该交织码在存储资源占用率、实时性相当情况下可靠性优于同等长度的SEC DED码,能有效提高SRAM型存储器抗多位翻转错误的能力。      

抗单粒子翻转效应的SRAM研究与设计

在空间应用和核辐射环境中,单粒子翻转(SEU)效应严重影响SRAM的可靠性。采用错误检测与校正(EDAC)和版图设计加固技术研究和设计了一款抗辐射SRAM芯片,以提高SRAM的抗单粒子翻转效应能力。内置的EDAC模块不仅实现了对存储数据"纠一检二"的功能,其附加的存储数据错误标志位还简化了SRAM的测试方案。通过SRAM原型芯片的流片和测试,验证了EDAC电路的功能。与三模冗余技术相比,所设计的抗辐射SRAM芯片具有面积小、集成度高以及低功耗等优点。     

抗单粒子翻转的双端口SRAM定时刷新机制研究

在空间辐射环境下,存储单元对单粒子翻转的敏感性日益增强。通过比较SRAM的单粒子翻转效应相关加固技术,在传统EDAC技术的基础上,增加少量硬件模块,有效利用双端口SRAM的端口资源,提出了一种新的周期可控定时刷新机制,实现了对存储单元数据的周期性纠错检错。对加固SRAM单元进行分析和仿真,结果表明,在保证存储单元数据被正常存取的前提下,定时刷新机制的引入很大程度地降低了单粒子翻转引起的错误累积效应,有效降低了SRAM出现软错误的概率。     

FPGA自主刷新技术研究

FPGA自主刷新技术是一种有效减缓FPGA单粒子翻转效应的措施,有利于提高FPGA空间应用时的可靠性。以Xilinx公司Virtex-7系列FPGA为例,研究基于内部配置访问接口(Internal Configuration Access Port,ICAP)对配置存储器的回读和刷新技术、基于帧纠错码(Frame Error Correction Code,FRAME_ECC)对配置存储器的检错和纠错技术等关键技术,使FPGA在空间应用时能够自主检测并纠正由于单粒子翻转造成的FPGA配置存储器位翻转错误,实现对每帧回读配置存储器数据中1比特位翻转错误的纠正及2比特位翻转错误的检测。     

量子逻辑门中的编码量子位研究

本文提出在量子编码中用量子字节控制量子字节的设想,具体分析了字节被控编码法防止或纠正逻辑运算错误的量子线路,该编码既适用于量子逻辑门的防错和纠错,也适用于防止量子计算机存储单元的解相干。该编码法量子位使用效率为５０％,且防错和纠错过程简单明了,并有单个逻辑双态双轨技术提供实验基础,因此该方案实现的可能性大。     

RS（16,12）缩短码编译码原理及性能分析

在各类数字通信系统以及计算机存储和运算系统经常利用差错控制编码降低误码率,提高通信质量,满足对数据传输通道可靠性的要求。RS码是一种性能优良的前向纠错码,具有同时纠正随机错误和突发错误的能力,它的构造特点决定了其非常适合于纠正突发性错误。文中在阐述RS系统码编译码原理的基础上,提出了RS（16,12）缩短码的编译码方法,利用MATLAB对R S（16,12）缩短码在高斯信道和瑞利信道条件下的纠错能力进行仿真,并分析其纠错性能。     

HDMI2.0接口FEC纠错模块设计

针对HDMI2.0中继器在传输数据的过程中数据因干扰会发生错误的问题,提出了采用前向纠错技术(FEC)来纠正控制周期数据错误而导致的错误视频和音频数据的方案,给出了FEC和HDMI2.0协议相结合的具体过程,实现了基于HDMI2.0接口的数据纠错模块的设计.在Cadence平台下,编写了可综合的Verilog代码实现了电路的设计,并用科学的测试方法对数据纠错模块进行了测试验证.验证结果表明:数据纠错模块和HDMI2.0接口有机地结合在一起,有效纠正了HDMI2.0中继器在数据传输过程中产生的错误,增强了数据传输的可靠性并提高了视听效果.     

一种基于编码的存储器加固设计

在太空辐射环境中存在各种宇宙射线和一些高能粒子,其中单粒子翻转（SEU）效应是引起存储器软错误的重要因素,降低了数据传输的可靠性,因此成为当前集成电路抗辐射加固设计的研究重点之一。标准的纠错编码（ECC）设计冗余度将占用超过50%的存储量,该设计基于缩短汉明码的原理实现了对32位存储器采用7位冗余码进行纠错编码的SEC-DED加固设计,在资源上得到了优化;同时从概率的角度分析了可靠性的理论基础,通过编码可靠性可以提高3到6个数量级。     

快速响应矩阵码纠错算法的研究

在研究纠错技术的基础上，采用高级语言，实现了快速响应矩阵码中基于伽罗华域GF（28）的Reed-Solomon编码和译码算法.在编码部分提出对国际标准中生成多项式的个数进行了压缩，有效实现各版本的生成多项式：对较大版本采用交错码技术，将错误离散，提高突发错误的纠正能力.实验表明，本算法实现了高效的纠错编码和译码。     

基于EDA的纠错编码及数据交织ASIC的设计

为了纠正数字通信中的随机错误和突发错误，提出了一种卷积编码和数据交织技术相结合的纠错编码方案，介绍了基于EDA技术的卷积纠错电路和数据交织器的设计方法，最终实现了利用MAX＋plusⅡ对纠错系统的设计集成，形成了卷积编码和数据交织ASIC。仿真表明，该方案工作稳定，纠错性能与单独的卷积纠错法相比有很大改善。     

Software-implemented EDAC protection against SEUs

In many computer systems, the contents of memory are protected by an error detection and correction (EDAC) code. Bit-flips caused by single event upsets (SEU) are a well-known problem in memory chips; EDAC codes have been an effective solution to this problem. These codes are usually implemented in hardware using extra memory bits and encoding/decoding circuitry. In systems where EDAC hardware is not available, the reliability of the system can be improved by providing protection through software. Codes and techniques that can be used for software implementation of EDAC are discussed and compared. The implementation requirements and issues are discussed, and some solutions are presented. The paper discusses in detail how system-level and chip-level structures relate to multiple error correction. A simple solution is presented to make the EDAC scheme independent of these structures. The technique in this paper was implemented and used effectively in an actual space experiment. We have observed that SEU corrupt the operating system or programs of a computer system that does not have any EDAC for memory, forcing the system to be reset frequently. Protecting the entire memory (code and data) might not be practical in software. However this paper demonstrates that software-implemented EDAC is a low-cost solution that provides protection for code segments and can appreciably enhance the system availability in a low-radiation space environment     

嵌入式存储器容错方案可靠性评估

随着工艺节点的不断降低,存储器的软错误率呈指数趋势上升,容错技术已成为存储器设计中的重要环节。依据美国NASA Rosetta实验数据,对错误检纠错码(EDAC: Error Detection and Correction)和不同的在线刷新模式组成的多种容错方案进行可靠性建模与量化评估,提出了不同工艺节点下嵌入式存储器容错技术选择的判据方法。在地面单粒子模拟实验中进行验证,结果表明,该方法预测的失效率评估结果与实验测试结果的平均偏差约为10.3%。     

Instruction-Vulnerability-Factor-Based Reliability Analysis Model for Program Memory

Bit faults induced by single-event upsets in instruction may not cause a system to experience an error. The instruction vulnerability factor (IVF) is first defined to quantify the effect of non-effective upsets on program reliability in this paper; and the mean time to failure (MTTF) model of program memory is then derived based on IVF. Further analysis of MTTF model concludes that the MTTF of program memory using error correcting code (ECC) and scrubbing is not always better than unhardened program memory. The constraints that should be met upon utilizing ECC and scrubbing in program memory are presented for the first time, to the best of authors’ knowledge. Additionally, the proposed models and conclusions are validated by Monte Carlo simulations in MATLAB. These results show that the proposed models have a good accuracy and their margin of error is less than 3 % compared with MATLAB simulation results. It should be highlighted that our conclusions may be used to contribute to selecting the optimal fault-tolerant technique to harden the program memory.     

Reliability of scrubbing recovery-techniques for memory systems

The authors analyze the problem of transient-error recovery in fault-tolerant memory systems, using a scrubbing technique. This technique is based on single-error-correction and double-error-detection (SEC-DED) codes. When a single error is detected in a memory word, the error is corrected and the word is rewritten in its original location. Two models are discussed: (1) exponentially distributed scrubbing, where a memory word is assumed to be checked in an exponentially distributed time period, and (2) deterministic scrubbing, where a memory word is checked periodically. Reliability and mean-time-to-failure (MTTF) equations are derived and estimated. The results of the scrubbing techniques are compared with those of memory systems without redundancies and with only SEC-DED codes. A major contribution of the analysis is easy-to-use expressions for MTTF of memories. The authors derive reliability functions and mean time to failure of four different memory systems subject to transient errors at exponentially distributed arrival times     

Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors

In this paper, we propose a diagnose strategy based on built-in current sensors able to detect the effects of single event transients (SETs) in SRAM memory decoders. By analyzing the effects, it is possible to mitigate the error by warning the system about the erroneous write and read operation or by circuit error correction avoiding catastrophic multiple bit upset errors. While EDAC can only protect faults in the memory cell array, the proposed method can cope with faults in the combinational memory circuitry. This BICS-based technique can be used in combination with EDAC to achieve high reliability in memories fabricated in nanometer technologies. Our methodology has been validated by Spice simulation and results show that our approach presents a low area, performance and power dissipation penalty.     

Low cost design of microprocessor EDAC circuit

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.     

Soft error recovery in simplex and triplex memory systems

This paper analyzes and compares the reliability and MTTF of four fault-tolerant memory configurations subject to soft errors, namely (i) the SEC protected RAM (SEC-RAM), (ii) the SEC-unprotected triplex RAM (TMR-RAM), (iii) the triplex SEC-protected RAM (TMR-SEC RAM) and (iv) the SEC-protected triplex RAM (SEC-TMR RAM). The last two configurations are new and their difference lies on the order of performing the voting and decoding operations. Depending on the configuration, memory modeling is accomplished by Markov models either at the bit or at the word level, by also taking into account the canceling of soft errors due to subsequent soft errors. Exact theoretical expressions for the reliability and MTTF of the SEC-RAM and TMR-RAM are developed and two alternative recursive algorithms are given to assess the impact of memory scrubbing on MTTF. The advantage of both the proposed configurations is that they can tolerate all possible error patterns with three errors and they also present a remarkable resistance to error patterns with a much larger number of errors. As the analysis of the SEC-TMR RAM cannot be accomplished theoretically, due to the varying error-patterns of the SEC decoder output for more than one error in a codeword, a fast error-pattern generation algorithm (FEP) is developed. Simulation results show that there exist numerous multiple-bit error patterns in more than two words in the SEC-TMR RAM that upon decoding and voting produce the correct data-word. A comparison of the multiple-bit error masking capability of the TMR-SEC and SEC-TMR is also given.     

Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint.     

ELIMINATING SPEED PENALTIES IN ECC PROTECTED MEMORY DESIGNS USING “BIT BYPASSING” TECHNIQUES

In deep sub-micron ICs,growing amounts of on-die memory and scaling effects make embedded memories more vulnerable to reliability problems,such as soft errors induced by radiation.Error Correction Code （ECC） along with scrubbing is an efficient method for protecting memories against these errors.However,the latency of coding circuits brings speed penalties in high performance applications.This paper proposed a ＂bit bypassing＂ ECC protected memory by buffering the encoded data and adding an identifying address for the input data.The proposed memory design has been fabricated on a 130 nm CMOS process.According to the measurement,the proposed scheme only gives the minimum delay overhead of 22.6％,compared with other corresponding memories.Furthermore,heavy ion testing demonstrated the single event effects performance of the proposed memory achieves error rate reductions by 42.9 to 63.3 times.