Electromigration reliability of interconnections in RF low noise amplifier circuit

With the continuous increase of the circuit complexity and the scaling down of the device size, electromigration (EM) failure in the interconnects has become the determining factor for circuit reliability. Most of the EM circuit simulators in the literature are at 2D level. The application of 2D simulators is limited as the actual physical implementation of the circuit in a wafer is indeed 3D in nature, and is much more complicated than 2D. In this paper, we construct a complete 3D circuit model of a RF low noise amplifier (LNA) circuit, including both the intra- and inter-block interconnects. Electric-thermal-structural simulations are performed and the modifications that help to enhance the EM reliability of the circuit are carried out based on the simulation results.     

Electromigration of silicon and phosphorus in tantalum polycide interconnections

TaSi2/n⁺-poly-Si interconnections of integrated circuits were investigated after high direct current density stress at elevated temperatures. The current density was increased up to values that caused failures of the interconnections due to electromigration. We found in our experiments that material migrated from the anode to the cathode causing open-circuit failure at the anode region. At the cathode, the material piled up forming hillocks. Material depletion and accumulation are caused by positive or negative mass flow divergences due to temperature gradients near the pads. The accumulated material at the cathode was analyzed by high-resolution Auger and SIMS spectroscopy. The obtained spectra show only silicon and phosphorus peaks with an increased phosphorus concentration at the cathode area. Hence, it can be concluded that in TaSi2/n⁺-poly-Si interconnection mainly material of the polysilicon layer including the dopant phosphorus is moved by electromigration. In contrast to these results of dc experiments, no electromigration occurred during equivalent ac stress.     

集成电路测试技术的应用研究

电子信息技术得到了很大的发展,从而促进了集成电路测试技术的广泛应用.因此,测试集成电路设计和制造的过程极其重要,要求相关工作人员对集成电路设计、制造的测试基本理论和方法必须熟练掌握,为高质量电子产品的生产提供保障.     

Electromigration and low-frequency resistance fluctuations in aluminum thin-film interconnections

Low-frequency noise spectra originating from resistance fluctuations in Al films during electromigration were measured in the absolute temperature and current density intervals327 leq T leq 396K and1.34 times 10^{6} leq j leq 2.22 times 10^{6}A/cm². The values of SR, the resistance power spectral density, at 20 × 10^-3Hz allowed the construction of an Arrhenius plot from which a grain-boundary activation energy value of about 0.6 eV was deduced. This value lies in the range of values found by other authors using different techniques. A first attempt to model the observed dependence of SRonjandTis also described.     

Electromigration detection by means of low-frequency noise measurements in thin-film interconnections

Low-frequency noise power spectral densities associated with displacements of atoms caused by electromigration were measured on Al-Si (1 percent) resistors at various current densities in the frequency range 5 × 10^{-2 ÷ 2}Hz. The temperature of the resistors was the one set by the current density itself, all the samples having been tested at room temperature. After noise measurement, each resistor was subjected to the current density at which the measurement was performed up to failure. The total electromigration power, measured in the frequency interval 0.1 ÷ 1 Hz was plotted as a function of the failure time for three different series of resistors obtained by means of an RF sputtering process. The measurement system and the characteristic features of the electromigration spectra are described.     

基于FPGA的集成电路测试系统设计探讨

随着集成电路的功能以及各种参数的大量增加,要想保证电路的可靠性,就必须重视集成电路的测试功能,在传统的测试过程中,对集成电路的测试是依靠有经验的测试人员使用信号发生器、万用表和示波器等仪器来进行测试的.这种测试方法测试效率低,无法实现大规模大批量的测试.为此,本文分析了基于FPGA集成电路测试系统的优越性,并选取某集成电路的老化测试系统设计为例进行重点探讨.     

Reflection and crosstalk in logic circuit interconnections

Digital logic circuits are now available and are being used with delay times that are comparable to the delays of interconnections used in packaging these circuits. At high speeds, however, such interconnections no longer behave as simple short circuits, but take on the appearance of transmission lines. Unless transmission lines are terminated properly, ``reflections' can develop that might be of sufficient magnitude to produce false logic levels or exceed maximum circuit voltage specifications. One may choose to solve the problem by increasing the density of the system. This, however, introduces the problem of ``crosstalk.' The present article describes several analytical techniques for predicting the kinds of reflections and crosstalk that are typically seen in digital systems, thus enabling the engineer to determine in advance whether or not such ``interconnection noise' will result, how bad it will be, and what the typical interconnection limitations are for circuits of various speeds.     

Novel broad-band bit-synchronization circuit module for optical interconnections

A novel broad-band and ultrafast bit-synchronization circuit module is proposed and fabricated for optical interconnections. In optical packet switch fabric or optical interconnection between electric circuit boards, instantaneous bit synchronization is crucial to properly retime incoming packets with a random phase and reduce the number of preamble overhead bits. The developed bit-synchronization circuit module has a new clock selection circuit, which is configured with a phase comparator and an amplitude comparator. Since device-dependent delay circuits, such as buffer amplifiers or RC phasors, are not adopted, the newly developed clock selection circuit can operate under broad-band frequencies. The bit-synchronization circuit module was fabricated with a Si-bipolar gate array and it can operate at broad-band bit rates of up to 10.5 Gb/s. It also exhibits a power sensitivity penalty as low as 3 dB for 10-Gb/s input signals. The synchronization acquisition time of less than 9 b over the entire 360/spl deg/ phase range was confirmed by experiment.     

MT-compatible laser-ablated interconnections for optical printed circuit boards

Integration of optical interconnections on a printed circuit board (PCB) is very challenging, since compatibility should be maintained with standard PCB manufacturing technology. This paper describes the use of laser ablation, a technique already used in PCB manufacturing for drilling microvias, as a suitable technique for the fabrication of multimode polymer waveguides, micromirrors, alignment features, and microlenses. A frequency-tripled Nd-YAG laser and a KrF excimer laser are used, both mounted on the same stage, resulting in very high alignment accuracies. This paper demonstrates a parallel optical link over approximately 5-cm-long PCB integrated waveguides, fully connected using a standard MT-based connector. This proves that laser ablation can be a key technology in optical board manufacturing to reach the stringent coupling tolerances.     

Improvement of integrated circuit testing reliability by using the defect based approach

The systematic decrease in the minimum feature size in VLSI circuits makes spot defects an increasingly significant cause of ICs’ faults. A testing method optimized for detecting faults of this origin has been recently developed. This method, called defect based testing (DBT), requires a lot of computational effort at the stage of testing-procedure preparation, which makes it appear less attractive than the well-known stuck-at-fault oriented testing. This paper, however, shows that a stuck-at-fault-optimized test-vector set may prove highly inefficient in detecting spot-defect-induced faults. Experiments with the C17 ISCAS-85 testability benchmark show that the risk of a spot-defect damaged circuit passing the test is dangerously high if the test set was designed with stuck-at-faults in mind. It is also shown that although spot defects may in some cases transform a combinational circuit into a sequential one, in practice this phenomenon does not require any special treatment from the test designer. Eventually, a few methods are discussed that make the DBT less time consuming.     

基于ISO14443A协议的RFID集成电路芯片测试系统的研究设计分析

基于ISO14443A协议的RFID集成电路芯片测试系统的设计研究对改善当前ATE的高成本、性能浪费等现象有积极意义。基于ISO14443A协议,利用RFID集成电路芯片设计了一个系统,从软硬件两个方面进行设计调试,并配合优化方案解决设计问题,最终结果表明设计系统运行效果佳,稳定性好,对于工业集成电路芯片测试系统的研究有一定价值。     

CMOS integrated circuit reliability

This paper summarizes recently published data on CMOS integrated circuit failure rates, and provides information on the effects of voltage, temperature, device complexity, and packaging on CMOS failure rates. Other factors which can affect failure rate are also indicated, including designs, materials, processes, in-process controls, screening tests, and product maturity. Data on failure rates of NMOS and PMOS integrated circuits are provided to enable comparison with CMOS data. It is concluded that available data do not indicate any consistent reliability difference for CMOS versus NMOS or PMOS integrated circuits. Because of the many advantages of CMOS integrated circuit technology, continued increase in usage of CMOS circuits has been forecast, accompanied by further increases in CMOS integrated circuit reliability.     

Statistical integrated circuit design

Several statistical design methods that have been developed to minimize the effects of IC manufacturing process disturbances on circuit performance are reviewed. It is shown that statistical design problems can be expressed as optimization problems in which either the objective function or the constraint functions depend on expectations of random variables. The effectiveness of the most recent such method, the boundary integral method is illustrated with several circuit design examples