Properties of ion-implanted junctions in mercury—cadmium—telluride

The formation of n-p junctions by ion-implantation in Hg0.71Cd0.29Te is shown to be a result of implantation damage. n-p photodiodes have been made by implantation of Ar, B, Al, and P in a p-type substrate with acceptor concentration of 4 × 10¹⁶cm^-3. The implanted n-type layer is characterized by sheet electron concentration of 10¹⁴to 10¹⁵cm^-2and electron mobility higher than 10³cm². V^-1. s^-1, for ion doses in the range 10¹³-5 × 10¹⁴cm^-2. The photodiodes have a spectral cutoff of 5.2 µm, quantum efficiency higher than 80 percent, and differential resistance by area product above 2000 Ω . cm²at 77 K. The temperature dependence of the differential resistance is discussed. The junction capacitance dependence on reverse voltage fits a linearly graded junction model. Reverse current characteristics at 77 K have been investigated using gate-controlled diodes. The results suggest that reverse breakdown is dominated by interband tunneling in field-induced junctions at the surface, for both polarities of surface potential.     

Surface state and surface recombination velocity characteristics of Si-SiO2interfaces

A new device has been used to study the surface recombination velocity and surface state characteristics of Si-SiO2interfaces. The device consists of an epitaxially-formed junction diode. When the junction is forward-biased, minority carriers are injected from the heavily-doped substrate into the lightly-doped epitaxial region. The thickness of the epitaxial region is much less than the diffusion length for minority carriers. Thus, the diode current for a given junction forward bias is directly proportional to surface recombination velocity at the Si-SioO2interface. A gate electrode over the SiO2has been included to vary surface potential. Thus, this new device permits one to simultaneously study MOS capacitance-voltage characteristics as well as surface recombination velocity. The capacitance-voltage characterics indicate the surface states exhibit a quasi-continuous energy distribution. N-type surfaces exhibited donor levels lying in the range of ∼0.15 to ∼0.45 eV above the valence band; their density was found to vary from ∼5 × 10¹²to 5 × 10¹³states/cm²/eV. In contrast, p-type surfaces exhibited acceptor levels lying in the range of ∼0.15 to ∼0.45 eV below the conduction band; their density was comparable to those observed on n-type surfaces. The maximum value of surface recombination velocity was found to vary from 3 × 10³to > 10⁴cm/s. Surface recombination velocity was found to correlate directly with surface state density.     

Evaluation of a Junction Termination Extension Avalanche Photodiode for X-Ray Detection

An avalanche photodiode (APD) with a ring structure around the active area was built. The junction termination extension (JTE) APD has three diffused rings around the main junction to reduce the electric field at the surface. This design has the advantage that it does not need a sharp bevel edge or grooves to avoid early breakdown at the surface. The JTE rings can be obtained by a well-controlled ion-implantation through a single mask. The process uses standard planar technology for silicon devices. Several APDs with 2-mm diameter active area have been built by implantation of boron with a dose of 2, 3, 4, and 5 x 10¹² cm^-2, followed by deep diffusion to 14 mum. The dark current is strongly dependent on the implantation charge, decreasing with decreasing charge. For the APDs with an implanted dose of 5 x 10¹² cm^-2, a gain of 8 is obtained at 1120 V, indicating that the devices have premature breakdown. The energy resolution from a 109Cd X-ray source (22.16 keV) was measured to be 4.7-keV full-width at half-maximum, which corresponds to 560 rms electrons noise. We have also performed simulations of the gain and breakdown voltage that correlate well with the results up to a gain of 5.     

Surface conduction in short-channel MOS devices as a limitation to VLSI scaling

In MOS VLSI device scaling, two major limiting mechanisms are the punchthrough and source-drain breakdown. The punchthrough mechanism is generally considered a bulk-dominated effect. Drain-source avalanche breakdown is generally attributed to bipolar transistor action between drain and source, dominated by injection through the neutral substrate region. The present work includes an experimental verification and a qualitative model demonstrating that both punchthrough and drain-source avalanche breakdown limitations are surface and surface-depletion-region dominated mechanisms, respectively. The two mechanisms are treated simultaneously since both involve enhanced injection from the source due to drain-induced source-potential barrier lowering. The experimental verification is done over a wide range of relevant device parameters, channel implant concentration between 5 × 10¹⁴-1 × 10¹⁶cm^-3for punchthrough and 2 × 10¹⁵-5 × 10¹⁶cm^-3for drain-source avalanche breakdown, effective channel length of 1.0-30.0 µm for both mechanisms.     

A precise MOSFET model for low-voltage circuits

A MOSFET model that is capable of handling the drain current above 10^-10A within the temperature range of 220-340 K is proposed. The key feature of the model is that surface potentials at source and pinchoff points are used for the purpose of obtaining a smooth connection between the current solutions in the tail and the saturation regions. Comparison of the model with experiments has been carried out using n-channel MOSFET's with 7 × 10¹³, 7 × 10¹⁴, and 4 × 10¹⁵cm^-3substrate impurity concentration and 675-, 1470-, and 5030-Å gate-oxide thickness. The theoretical calculations are in excellent agreement with the experimental measurements. It is shown that low-level current has a strong influence on the low-voltage static inverter circuit and dynamic memory.     

In-situ low energy BF2+ion doping for silicon molecular beam epitaxy

An experimental study of the p-type ion dopant BF2+ in silicon molecular beam epitaxy (MBE) is described. BF2+ was used to dope MBE layers during growth to levels ranging from 1 × 10¹⁶/cm³to 4 × 10¹⁸/cm³over a growth temperature range of 650°C to 1000°C. The layers were evaluated using spreading resistance, chemical etching, and secondary ion mass spectroscopy. Complete dopant activation was observed for all growth temperatures. Remnant fluorine in the epitaxial layer was less than 2 × 10¹⁶/cm³in all cases. Diffused p-n junction diodes fabricated in BF2+-doped epitaxial material showed hard reverse breakdown characteristics.     

A planar InP/InGaAs avalanche photodiode with floating guard ringand double diffused junction

The authors discuss the fabrication, performance, and design of a novel, planar In_0.53Ga_0.47 As/InP separate absorption and multiplication region avalanche photodiode (SAM-APD) with floating guard rings and a double Zn diffused junction. The APD, grown by both vapor phase epitaxy and metalorganic vapor phase epitaxy, is observed to have a uniform gain of 85, a minimum primary dark current density of 5×10^-6 A/cm² at 90% of breakdown, and a capacitance of 0.4 pF for a front-side illuminated device. Both experimental and analytical results show that the double-diffused floating guard ring structure prevents edge breakdown, and also greatly reduces the electric field along the semiconductor/insulator surface. The operation mechanisms and the optimum design of the planar APD based on a two-dimensional device model are discussed     

Optical microprobe response of GaAs diodes

GaAs p-n junction photocurrent response is obtained from an optical microprobe with a dynamic range of at least three decades and a light-spot diameter of about 1.3 µm. The results are found to correlate well with the appropriate theoretical response which includes surface recombination and assumed infinite absorption coefficient. Minority-carrier diffusion lengths computed from the data are typically 3.5 and 0.7 µm for holes in n-type material doped 10¹⁷and 1.4×10¹⁸cm^-3and 1 µm for electrons in >10¹⁸cm^-3doped p-type material. Estimates of carrier lifetimes are made and the deviation of surface recombination velocity between devices is demonstrated.     

High value implanted resistors for microcircuits

Boron ion implantation has been used to fabricate high sheet resistance p-type junction resistors in silicon substrates. Thermally grown SiO2and conventional photolithography were employed to define the resistor geometries. Ion doses in the range 0.5 × 10¹³to 10 × 10¹³ions/cm²with energies ranging from 30 to 55 keV followed by anneal at 950°C were used. The temperature coefficient of resistance (TCR), voltage coefficient of resistance (VCR), junction Characteristics, and noise level of these resistors have been studied for sheet resistances ρx, from 0.8 to 11 kΩ/square. Over this range of sheet resistances the TCR increases smoothly from approximately 800 to 4000 PPM/°C with the lower TCR corresponding to the lower sheet resistance. For 3 kΩ square implanted resistors, the variation of resistance with temperature closely matches that found for a standard boron base and resistor (B&R) diffusion having a sheet resistance of 140 Ω/square. The junction leakage and the noise level of the implanted resistors can be made comparable to that obtained for diffused resistors. The implanted resistor exhibits a positive VCR, which increases with increasing sheet resistance as a result of depletion-layer pinch-off action from the substrate. Details of the implant conditions and process control are discussed. Experimental results demonstrating the compatibility of the resistor implantation process with microcircuits using low current, high β diffused bipolar transistors are presented.     

Maximum rapidly-switchable power density in junction triodes

The maximum power density which may be switched at (switching time/current gain) quotients comparable to 1/2πfαis shown to be 10⁵- 4 × 10⁵watts/cm²for p-n-p germanium transistors. This result is derived first for junction triodes in which the collector depletion layer at peak reverse voltage lies largely in a collector body of conductivity type opposite to that of the base; e.g., diffused base transistors of the mesa type. The limitation arises from the linear dependence of maximum (scattering limited) current density(J_{max})on collector-body impurity concentration(N_{Ac})and from the approximately reciprocal dependence of breakdown voltage(BV_{CB})on the same parameter. It is shown that space-charge limitation of current dennsity leads to a somewhat lower limit for intrinsic collector barriers of the same maximum width and, a fortiori, to a lower value for collector barriers lying largely in material of the same conductivity type as the base layer. Similar limits for n-p-n germanium and for silicon transistors are higher but generally comparable.     

Electronic properties of the silicon-thermally grown tantalum oxide interface

MOS capacitance measurements showed that the Si-Ta2O5interface prepared by thermal oxidation at ∼530°C of vacuum deposited Ta film followed by a heat treatment at 350°C in N2-H2is characterized by a negative "oxide" charge (6 × 10¹¹e/cm^-2at flat-band) and by an interface state density of ∼ 1 × 10¹²cm^-2(eV)^-1. The room temperature instability is small. The breakdown strength is >8 × 10⁶V/cm.     

The anomalous avalanche breakdown

Normally, the breakdown voltage of a p-n junction decreases with increasing doping density. But there are also cases in which the breakdown voltage increases with increasing doping density, e.g., for InSb in the doping range from 10¹³cm^-3to 2 × 10¹⁴cm^-3. The reason for the anomalous behavior is the saturation of the ionization coefficient with increasing electric field strength. The anomalous behavior can only be observed if the tunnel breakdown requires a higher field strength as the one required for saturation of the ionization coefficient. This paper presents a rather simple theory yielding analytical solutions for the normal and anomalous avalanche breakdown. Treated is the influence of the doping profile upon the breakdown voltage in plane junctions and the influence of the radius of curvature for cylindrical one-sided abrupt junctions. The influence of the temperature upon the breakdown voltage and the multiplication factor as function of voltage is calculated for one-sided abrupt plane junctions. Finally, the temperature and doping range for the anomalous avalanche breakdown and the transition region is plotted for the semiconductors InSb, InAs, CdHgTe, PbSnTe, Ge, Si, GaAs, and GaP.     

SOLID-II: High-voltage high-gain kilo-Ångstrom-channel-length CMOSFET's using Silicide with self-aligned ultrashallow (3S) junction

A simple novel pile-up phenomenon which leads to an available layered structure of silicide with self-aligned ultrashallow (3S) junction is described. Heavily piled-up impurity (P or B) layers less than 50 nm deep under refractory metal (Ti, W, or Pd) silicide accomplish excellent p-n junction characteristics. Good ohmic properties are also obtained with contact resistivity less than 4 × 10^-6ω cm²independent of substrate concentration. This notable profile can easily be realized when a high dose (≥ 5 × 10¹⁵cm^-2) of impurity is implanted not through but into the refractory metal without intermixing, and followed by Silicidation. An application of this new phenomenon for a kilo-Ångstrom-channel-length CMOSFET is also proposed and evaluated using two-dimensional numerical simulation. In the advanced device, silicide on lightly doped drain II (SOLID-II), the breakdown voltage and current gain product of kilo-Ångstrom-channel-length MOSFET's with 3S junction can be significantly improved in comparison with those of conventional LDD devices. In the 0.3-µm-channel-length devices, current gain reduction in SOLID-II is less than 10 percent compared with that in the standard device. However, in the LDD more than a 20-percent reduction is unavoidable with the same breakdown voltage of 8.5 V. It is proved that the SOLID-II: structures can be used very effectively as a 0.2-0.5-µm-channel-length CMOSFET operatable with 5-V power supply.     

Leakage current characteristics of offset-gate-structure polycrystalline-Silicon MOSFET's

Leakage current characteristics of offset-gate-structure polycrystalline-silicon (poly-Si) MOSFET's are studied as a function of dopant concentration Noffin offset-gate regions. Leakage current markedly decreases from 1 × 10^-9to 2 × 10^-11A at VD= 10 V as Noffis varied from 1 × 10¹⁸to 1 × 10¹⁷cm^-3. A maximum ON/OFF current ratio of 10⁸is obtained at 1 × 10¹⁷cm^-3. Calculations based on a quasi-two-dimensional model indicate that the reduction of leakage current is attributable to a decrease of the maximum lateral electric field strength in the drain depletion region. An analysis of the leakage current characteristics in terms of carrier emission from grain-boundary traps implies that thermonic emission accompanied by thermally assisted tunneling could be the dominant mechanism in determining leakage current.     

Limitations on injection efficiency in power devices

In this paper the mechanisms of bandgap narrowing, Shockley-Read-Hall (SRH) recombination, Auger recombination, and carrier-carrier and carrier-lattice scattering are included in an exact one-dimensional model of a bipolar transistor. The transistor is used as a vehicle for studying the relative importance of each of these phenomena in determining emitter efficiency in devices with emitter junction depths of 1 µm to 8 µm. It is shown that bandgap narrowing is the dominant influence for devices with shallow emitters of 2 µm or less and that SRH recombination dominates for emitter depths greater than 4 µm. Calculations are also presented showing the effects of the emitter surface concentration and high-level injection on the current gain for devices with emitter junction depths of 1 µm to 8 µm. It is shown that there is an optimum surface concentration of 5 × 10¹⁹cm^-3for the 1-µm emitter depth but no optimum under 10²¹cm^-3for devices with emitter depths greater than 4 µm.     

Modeling of substrate current in p-MOSFET's

It is shown that the substrate current characterization method and modeling approach used for n-MOSFET's is also applicable to p-MOSFET's. The impact ionization rate extracted for holes is found to be 8 × 10⁶exp (-3.7 × 10⁶/E), where E is the electric field. Based on our measurement and modeling result, roughly twice the channel electric field is required for p-MOSFET's to generate the same amount of substrate current as n-MOSFET's. The hot-carrier-induced breakdown voltage is therefore also about two times larger.     

Avalanche phenomena in 4H-SiC p-n diodes fabricated by aluminum orboron implantation

Characteristics of p-n junction fabricated by aluminum-ion (Al⁺) or boron-ion (B⁺) implantation and high-dose Al⁺-implantation into 4H-SiC (0001) have been investigated. By the combination of high-dose (4×10¹⁵ cm^-2) Al⁺ implantation at 500°C and subsequent annealing at 1700°C, a minimum sheet resistance of 3.6 kΩ/□ (p-type) has been obtained. Three types of diodes with planar structure were fabricated by employing Al+ or B+ implantation. B ⁺-implanted diodes have shown higher breakdown voltages than Al⁺-implanted diodes. A SiC p-n diode fabricated by deep B+ implantation has exhibited a high breakdown voltage of 2900 V with a low on-resistance of 8.0 mΩcm² at room temperature. The diodes fabricated in this study showed positive temperature coefficients of breakdown voltage, meaning avalanche breakdown. The avalanche breakdown is discussed with observation of luminescence     

Elimination of the guard ring in uniform avalanche photodiodes

A conventionalp^{+}-n(orn^{+}-p) planar avalanche photodiode with a 10^-4cm²active area has ∼2.5 × 10^-4cm²total area because of its protecting guard ring and has a series resistance of ∼50 to 100 ohms. For narrow-band applications, multiplications greater than 10 are necessary to equal the available output power of a conventional nonavalanchingp-i-nphotodiode. In broad-band applications, significant multiplications are necessary to compete favorably with thep-i-nwhen the active area is less than 10^-4cm²or when the signal frequency is > 1 GHz. Ap-n^{+}planar structure is discussed that eliminates the need for a guard ring because positive junction curvature occurs on the high-resistivity side. Thep-n^{+}diodes can be designed to have resistances (Rs∼2 ohms), capacitances (C < 1 pf), and RC cutoff frequencies (fco>100 GHz) equivalent to those of thep-i-nand to have uniform multiplication as well. Closer array spacings can be achieved than with the guard ring structure, as well as higher effective quantum efficiencies in the avalanche mode. Practical realization of thep-n^{+}structure has been achieved in silicon by a combination of epitaxial and doped-oxide processing. Seven-mil-diameter junctions with high breakdown voltage (110 V) and uniform avalanche properties have been constructed.     

Turnover phenomenon in N ν N Si devices and second breakdown in transistors

Turnover phenomenon in N νl N Si devices was studied in relation to second breakdown in NP ν N Si transistors. The devices were fabricated by a usual diffusion method using P2O5powder as diffusant source. Four groups of the devices, each having a diameter of 1.0 mm, a thickness of 0.25 mm, a resistivity in ν layer ranging from 3 to 210 ohm-cm, and a surface concentration in N layer of 2 × 10²⁰cm^-3, were tested under two kinds of applied voltage. The applied voltage was a half-cycle voltage from ac source and single-pulse voltage with a rising and flat part. The field strength in ν layer was below 3 × 10³v/cm. The voltage vs. current characteristics and the transient figures of voltage and current were observed on a memoriscope, and the temperature of the device was determined using temperature sensitive paints. The current increases linearly with the increasing voltage at the onset of the V-I curve, and saturates with further increases in voltage. Turnover occurs after the large departure from ohmic behavior in V-I characteristics. At the turnover, the temperature of the device was estimated to be near intrinsic; 160°C for the device with ∼ 210 ohm-cm, 330°C for ∼ 3 ohm-cm. The discussions on turnover characteristics are made in terms of the decrease in carrier mobility, the increase in carrier concentration in ν layer, and the current constriction in the device.     

A high-current drivability i-AlGaAs/n-GaAs doped-channel MIS-Like FET (DMT)

A high-current drivability doped-channel MIS-like FET (DMT) has been proposed. The DMT takes advantage of high saturation current with large transconductance and high breakdown voltage, in regard to its operating principle. The fabricated 0.5-µm gate DMT showed 310-mS/mm (410-mS/mm) transconductance and 650-mA/mm (800-mA/mm) maximum saturation current at room temperature (at 77 K). Output current values are about three or four times those for conventional two-dimensional electron gas (2DEG) FET's. Estimated average electron velocity is rather high, 1.5 × 10⁷cm/s (2 × 10⁷cm/s) at room temperature (77 K). In addition,f_{max}is as high as 41 GHz. fTis 45 GHz, which is the best data ever reported in 0.5-µm gate FET's.