Delay time analysis for 0.4- to 5-μm-gate InAlAs-InGaAs HEMTs

InAlAs-InGaAs HEMTs with 0.4- to 5-μm gate lengths have been fabricated and a maximum f_T of 84 GHz has been obtained by a device with a 0.4-μm gate length. A simple analysis of their delay times was performed. It was found that gradual channel approximation with a field-dependent mobility model with E_c of 5 kV/cm holds for long-channel devices (L _g>2 μm), while a saturated velocity model with a saturated velocity of 2.7×10⁷ cm/s holds for short-channel devices (L_g<1 μm)     

Electron transport in 0.15-μm gate In0.52Al0.48As/In0.53Ga0.47As HEMT

Magneto-transport and cyclotron resonance measurements were made to determine directly the density, mobility, and the effective mass of the charge carriers in a high-performance 0.15-μm gate In_0.52 Al_0.48As/In_0.53Ga_0.47As high-electron-mobility transistor (HEMT) at low temperatures. At the gate voltage V_G=0 V, the carrier density n _g under the gate is 9×10¹¹ cm^-2, while outside of the gate region n_g=2.1×10¹² cm^-2. The mobility under the gate at 4.2 K is as low as 400 cm²/V-s when V_G<0.1 V and rapidly approaches 11000 cm²/V-s when V_G>0.1 V. The existence of this high mobility threshold is crucial to the operation of the device and sets its high-performance region in V_G>0.1 V     

InGaAs metal-semiconductor field-effect transistor withLangmuir-Blodgett deposited gate structure

A high-transconductance n-channel, depletion-mode InGaAs metal-semiconductor field-effect transistor (MESFET) with a Langmuir-Blodgett deposited gate fabricated on organometallic chemical vapor deposition (OMCVD)-grown InGaAs lattice matched to InP is reported. The fabrication process is similar to epitaxial GaAs FET technology and is suitable for making optoelectronic integrated circuits (OEICs) for long-wavelength fiber-optic communications systems. Devices with 1-μm gate and 6×10¹⁶ channel doping achieved 162-mS/mm extrinsic transconductance and -1.8-V pinch-off voltage. The effective saturation velocity of electrons in the channel was measured to be between 3.5 and 3.9×10⁷ cm/s. The drain current ( I_dss), 300 mA/mm at V_ds=2.5 V, is the highest current capability reported for depletion-mode InGaAs MESFET devices with low pinch-off voltages     

Ultrahigh-frequency performance of submicrometer-gate ion-implantedGaAs MESFETs

A study of the high-frequency performance of short-gate ion-implanted GaAs MESFETs with gate lengths of 0.3 and 0.5 μm is discussed. Excellent DC and microwave performance have been achieved with an emphasis on the reduction of effective gate length during device fabrication. From f_t of 83 and 48 GHz for 0.3-0.5-μm gate devices, respectively, an electron velocity of 1.5×10⁷ cm/s is estimated. An f_t of 240 GHz is also projected for a 0.1-μm-gate GaAs MESFET. These experimental results are believed to be comparable to those of the best HEMTs (high-electron-mobility transistors) reported and higher than those generally accepted for MESFETs     

High-performance submicrometer undergated thin-film transistorswithout high-temperature rapid thermal annealing or plasma hydrogenation

High-performance submicrometer undergated thin-film transistors (TFTs) are fabricated without using high-temperature rapid thermal annealing or plasma hydrogenation. These processes are used in the state-of-the-art devices, but avoided in current manufacturing. For a 0.35-μm×0.35-μm device and a 0.7-μm×0.5-μm device, I_ON of 3 and 1.2 μA are obtained with ON/OFF current ratios of 4×10⁵ and 1.2×10⁸ , respectively, very close to that of state-of-the-art devices. A new lightly-doped-drain (LDD) structure is employed to improve I_ON reproducibility, which is difficult to achieve for deep-submicrometer devices with the conventional lightly-doped-offset (LDO) structure     

High-transconductance insulating-gate InP/InGaAs buried p-bufferDH-MODFETs grown by MOVPE

Buried p-buffer double heterostructure modulation-doped field-effect transistors (BP DH-MODFETs) with an InGaAs quantum-well channel were fabricated with high transconductance and good breakdown voltage, by placing the metal gate directly on Fe-doped InP insulating layer. Excellent extrinsic DC transconductance of 560 mS/mm and a high gate-to-drain diode breakdown voltage (greater than 20 V) were achieved at room temperature with FETs of 1.2-μm gate length. Unity currently gain cutoff frequency f_T of 24 GHz and maximum oscillation frequency f_max of 60 GHz were demonstrated for a drain to source voltage V_DS=4 V, which corresponds to an average electron velocity of 2.2×10⁷ cm/s in the quantum well     

Gate-controlled negative differential resistance in drain currentcharacteristics of AlGaAs/InGaAs/GaAs pseudomorphic MODFETs

The observation of negative differential resistance (NDR) and negative transconductance at high drain and gate fields in depletion-mode AlGaAs/InGaAs/GaAs MODFETs with gate lengths L _g ~0.25 μm is discussed. It is shown that under high bias voltage conditions, V_ds>2.5 V and V_gs>0 V, the device drain current characteristic switches from a high current state to a low current state, resulting in reflection gain in the drain circuit of the MODFET. The decrease in the drain current of the device corresponds to a sudden increase in the gate current. It is shown that the device can be operated in two regions: (1) standard MODFET operation for V_gs<0 V resulting in f_max values of >120 GHz, and (2) a NDR region which yields operation as a reflection gain amplifier for V_gs >0 V and V_ds>2.5 V, resulting in 2 dB of reflection gain at 26.5 GHz. The NDR is attributed to the redistribution of charge and voltage in the channel caused by electrons crossing the heterobarrier under high-field conditions. The NDR gain regime, which is controllable by gate and drain voltages, is a new operating mode for MODFETs under high bias conditions     

Si/a-Si:H heterojunction microwave bipolar transistors with cut-offfrequencies ft above 5 GHz

The fabrication of a silicon heterojunction microwave bipolar transistor with an n⁺ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V_CE=6 V, I_c=15 mA), and an emitter Gummel number G _E of about 1.4×10¹⁴ Scm^-4. From the measured S parameters, a cutoff frequency f_t of 5.5 GHz and maximum oscillating frequency f_max of 7.5 GHz at V_CE=10 V, I_c=10 mA are obtained     

A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V_ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency (f_T) of 14 GHz with a collector-emitter breakdown voltage (BV_CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f_T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process     

Reduction of channel hot-electron-generated substrate current insub-150-nm channel length Si MOSFET's

Channel hot-electron-generated substrate currents were measured in MOSFET devices with channel lengths down to 0.09 μm, and a family of characteristic plots of substrate current, normalized to drain current, I_SUB/I_D, rather than (V _DS-V_DSAT)^-1 was obtained. For channel lengths greater than 0.5 μm, the characteristics are independent of channel length. For channel lengths in the range of 0.15 μm, the characteristics are independent of channel length. For channel lengths in the range of 0.15 μm, the normalized substrate current at constant V_DS increases with decreasing channel length. However, as the channel length is decreased below 0.15 μm, a decrease of the normalized substrate current is observed. The decrease is larger at 77 K than at 300 K. This decrease accompanies the onset of electron velocity overshoot over a large portion of the channel. It is suggested that the decrease is due either to a decrease of carrier energy because energy relaxation and transit times become comparable, to a relative decrease of the carrier population in the channel, or to both     

Doubly strainedIn0.41Al0.59As/n+-In0.65Ga0.35As HFET with high breakdown voltage

An In_0.41Al_0.59As/n⁺-In_0.65 Ga_0.35As HFET on InP was designed and fabricated, using the following methodology to enhance device breakdown: a quantum-well channel to introduce electron quantization and increase the effective channel bandgap, a strained In_0.41Al_0.59As insulator, and the elimination of parasitic mesa-sidewall gate leakage. The In_0.65Ga_0.35As channel is optimally doped to N_D=6×10¹⁸ cm^-3. The resulting device (L_g=1.9 μm, W_g =200 μm) has f_t=14.9 GHz, f_max in the range of 85 to 101 GHz, MSG=17.6 dB at 12 GHz V_B=12.8 V, and I_D(max)=302 mA/mm. This structure offers the promise of high-voltage applications at high frequencies on InP     

A high-speed and highly uniform submicrometer-gate BPLDD GaAsMESFET for GaAs LSIs

The authors present formation conditions for ion-implanted regions of a GaAs buried p-layer lightly doped drain (BPLDD) MESFET that can improve short-channel effect, V_th uniformity, and FET operating speed, simultaneously. For 0.7-μm gates, a Mg⁺ dose of 2×10¹² cm^-2 at 300 keV and a Si⁺ dose of 2×10¹² cm^-2 at 50 keV are suitable for the p layer and n' layer, respectively. A σV _th of 7 mV is realized. Gate-edge capacitance of the 0.7-μm-gate BPLDD that consists of both overlap capacitance and fringing capacitance is successfully reduced to 0.5 fF/μm, which is about 50% of that of a non-LDD buried p-layer (BP) FET. Another parasitic capacitance due to the p-layer was found to have less effect on the speed than the gate-edge one. Consequently, the gate propagation delay time of the BPLDD can be reduced to 15 ps at power dissipation of 1 mW/gate, which is about 65% of that of a BP. Applying the 0.7-μm-gate BPLDD to 16-kb SRAMs, the authors have obtained a maximum access time of less than 5 ns with a galloping test pattern     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

An anisotype GaAs/InxGa1-xAs heterojunctionfield-effect transistor for digital logic applications

An anisotype heterojunction field-effect transistor (A-HJFET) for GaAs digital integrated circuit applications is proposed. A thin, highly doped, strained In_xGa_1-xAs (x⩽0.2) n-channel is employed for improved transconductance while a p⁺-GaAs cap is used to enhance the dynamic gate voltage range of the device. Prototype devices with 5-μm gate lengths show a maximum transconductance of 80 mS/mm at V_ds=2 V and a forward gate bias voltage of up to +2 V without significant leakage current     

Microwave performance of ion-implanted InP JFETs

These devices have a planar structure with the channel and gate regions formed by the selective implantation of silicon and beryllium into an Fe-doped semi-insulating InP substrate. The nominal gate length is 2 μm with a channel doping of 10¹⁷ cm^-3 and thickness of 0.2 μm. The measured values of f_T and f_max are 10 and 23 GHz, respectively. Examination of the equivalent circuit parameters and their variation with bias led to the following conclusions: (a) a relatively gradual channel profile results in lower than desired transconductance, but also lower gate-to-channel capacitance; (b) although for the present devices, the gate length and transconductance are the primary performance-limiting parameters, the gate contact resistance also reduces the power gain significantly; (c) the output resistance appears lower than that of an equivalent GaAs MESFET, and requires a larger V_DS to reach its maximum value; and (d) a dipole layer forms and decouples the gate from the drain with a strength that falls between that of previously reported GaAs MESFETs and InP MESFETs     

Charge control, DC, and RF performance of a 0.35-μmpseudomorphic AlGaAs/InGaAs modulation-doped field-effecttransistor

The authors describe a study of charge control in conjunction with DC and RF performance of 0.35-μm-gate-length pseudomorphic AlGaAs/InGaAs MODFETs. Using C-V measurements, they estimate that a two-dimensional electron gas (2DEG) with density as high as 1.0×10¹² cm^-2 can be accumulated in the InGaAs channel at 77 K before the gate begins to modulate parasitic charges in the AlGaAs. This improvement in charge control of about 10-30% over a typical AlGaAs/GaAs MODFET may partially be responsible for the superior DC and RF performance of the AlGaAs/InGaAs MODFET. At room temperature, the devices give a maximum DC voltage gain g _m/g_d of 32 and a current gain cutoff frequency f_T of 46 GHz. These results are state of the art for MODFETs of similar gate length     

A 1-μm polysilicon self-aligning bipolar process for low-powerhigh-speed integrated circuits

A double-poly-Si self-aligning bipolar process employing 1-μm lithography is developed for very-high-speed circuit applications. Epilayer doping and thickness are optimized for breakdown voltages and good speed-power performance. Shallow base-emitter profiles are obtained by combining low-energy boron implantation and rapid thermal annealing (RTA) for the emitter drive-in. A transit frequency f_T =14 GHz at V_BC=-1 V and a current-mode-logic (CML) gate delay of 43 ps at 30 fJ are achieved. For an emitter size of 1.0×2.0 μm² a minimum power-delay product of 15 fJ is calculated. Circuit performance capability is demonstrated by a static frequency divider operating up to 15 GHz     

High-speed performance of Si/Si1-xGexheterojunction bipolar transistors

A theoretical investigation of Si/Si_1-xGe_x heterojunction bipolar transistors (HBTs) undertaken in an attempt to determine their speed potential is discussed. The analysis is based on a compact transistor model, and devices with self-aligned geometry, including both extrinsic and intrinsic parameters, are considered. For an emitter area of 1×5 μm², an f_t of over 75 GHz and f_max of over 35 GHz were computed at a collector current density of 1×10 ⁵ A/cm² and V_CB of 5 V     

High-performance dual-gate CMOS utilizing a novel self-alignedpocket implantation (SPI) technology

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi₂ film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L_g (the physical gate length) is 0.21 μm for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21-μm gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5×10 ¹⁶ cm^-3). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 μm, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 μm     

Characteristics of field-induced-drain (FID) poly-Si TFTs with highon/off current ratio

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with a field-induction-drain (FID) structure using an inversion layer as a drain are investigated. The FID structure not only reduces the anomalous leakage current, but also maintains a high on current. An off current of 1.5 pA/μm and an on/off current ratio of 10⁷ (V_d=10, V_g =-20 V) are successfully obtained. These characteristics result from good junction characteristics between the p channel and n⁺ inversion layer. Reducing the threshold voltage of the FID region allows a simple circuit configuration for the FID TFTs