微系统热阻模型研究及其应用

系统级封装(SIP)实现了高密度、高集成度封装技术,同时散热问题备受关注,热设计中芯片结温预测十分重要.本文采用有限元仿真方法,建立了一种自然对流环境下微系统热阻模型,并通过模型中热阻矩阵预测多芯片总功耗相同条件下的各芯片结温,同时利用热阻测试试验和有限元仿真方法对预测结温进行验证,结果表明热阻矩阵模型预测芯片结温与热阻测试试验和有限元仿真结果误差分别小于2%和5%.但同时发现该热阻矩阵模型的不通用性,对于总功耗变化的多芯片结温,预测结果偏差较大.通过不同总功耗下各热阻矩阵的函数关系建立拟合曲线并修正热阻矩阵模型,修正后的结环境热阻矩阵适用于不同总功率条件、各芯片不同功率条件下的芯片结温预测,预测结果与热阻测试试验中芯片结温和有限元仿真结果误差均小于5%.因此,提出的修正结环境热阻矩阵的方法可以快速且便捷地预测不同功率芯片的结温,并对器件的散热性能进行较为准确的预估.     

大功率LED结温测量及发光特性研究

介绍了基于正向电压法原理自行研制的大功率LED结温测试系统,结温定量测量精度可达±0.5 ℃.利用该系统对不同芯片结构与不同封装工艺的大功率LED热阻进行了测量比较,并对不同结温的大功率LED发光特性进行了研究.结果表明,不同结构芯片温度-电压系数K明显不同;采用热导率更高的粘结材料和共晶焊工艺固定LED芯片,会明显降低封装层次引入的热阻.结温对光辐射功率有直接影响,若保持结温恒定,光辐射功率随电流增大线性增加;若保持外部散热条件不变,热阻大的芯片内部热量积累较快,导致结温上升速度更快,光效随电流增加而下降的趋势也更为严重.     

薄栅CMOS的可靠性模型

介绍了两种与栅氧化层失效有关的模型以及用于估计芯片寿命的热阻模型.随着晶体管特征尺寸的减小,现有的栅失效模型不能提供准确的计算和预测,因此提出了新的适用于小尺寸晶体管的栅失效模型.同时提出了用于评价芯片寿命的热阻和结温的估计模型.     

薄栅CMOS的可靠性模型

介绍了两种与栅氧化层失效有关的模型以及用于估计芯片寿命的热阻模型.随着晶体管特征尺寸的减小,现有的栅失效模型不能提供准确的计算和预测,因此提出了新的适用于小尺寸晶体管的栅失效模型.同时提出了用于评价芯片寿命的热阻和结温的估计模型.     

薄栅CMOS的可靠性模型

介绍了两种与栅氧化层失效有关的模型以及用于估计芯片寿命的热阻模型. 随着晶体管特征尺寸的减小，现有的栅失效模型不能提供准确的计算和预测，因此提出了新的适用于小尺寸晶体管的栅失效模型. 同时提出了用于评价芯片寿命的热阻和结温的估计模型.     

多芯片贴片式LED器件结温测量

结温是多芯片LED器件热性能的关键参数。以SMD5050 LED器件为例,研究了多芯片贴片式LED器件结温测量方法。SMD5050 LED是一种多芯片贴片式封装的LED器件,器件内封装有3颗芯片,3颗芯片之间并联。根据单芯片LED器件热阻测试原理,模拟SMD5050 LED器件正常工作时的状态,对SMD5050 LED器件的结温进行了测量,并根据LED芯片特性,验证了测量结果的准确性,这种方法适用于封装结构相似的其他多芯片LED器件结温的测量。     

基于表面响应法的半导体器件热阻网络技术研究

热阻网络是在扩展传统内热阻定义的基础上,将计算机模拟的全模型采用优化方法简化而得到的。该方法继承了全模型可预测在各种工作环境下的芯片结温的优点。在分析半导体器件内热阻的基础上,提出了一种新的独立于边界条件的热阻网络模型,并运用表面响应法,建立VCM(Valid Chip Model)的热阻网络模型。通过验证,该模型具有很高的精确度,适用于复杂的系统级热设计。     

采用动态差分模型表征脉冲驱动LED电热特性

为了研究不同驱动方式下LED结温的差异性,依据LED热结构模型,从功率传递角度构建了差分型LED电-热动态模型,利用相同平均功率、不同频率的注入电功率,计算脉冲驱动条件下的LED结温.同时,采用正向电压法测量实际结温,对模型预测结温的准确性进行了分析.研究表明,差分模型能够表征脉冲驱动方式下LED电热特性,其理论预测值与实测值误差约为4℃,基本能够满足工程应用要求.更有意义的是,采用差分模型,能够分析在特定驱动条件下,LED热容、热阻等参数对结温的影响,为不同驱动模式下LED个性化结构设计提供了理论基础.     

混合集成电路常见装配结构热阻分析

从常规电子产品热设计基础理论的理解分析入手,结合实际应用,阐述了混合集成电路典型装配结构热阻的简便分析方法;绘制了多种典型结构的内热阻与发热芯片面积的关系曲线和外热阻与封装表面积的关系曲线;提出了通过典型结构热阻曲线分析产品芯片结温的方法,及相应问题的处理办法;对一般混合集成电路的非精确热设计有一定的参考意义。     

基于石墨嵌入式结构的SiC功率模块热仿真与优化

SiC器件相比于Si器件,具有更高的功率密度,表现出高的器件结温和热阻。为了提高SiC功率模块的散热能力,提出了一种基于石墨嵌入式叠层DBC的SiC功率模块封装结构,并建立封装体模型。通过ANSYS有限元软件,对石墨层厚度、铜层厚度和导热铜柱直径进行分析,研究各因素对散热性能的影响,并对封装结构进行优化以获得更好的热性能。仿真结果表明,石墨嵌入式封装结构结温为61.675℃,与传统单层DBC封装相比,结温降低19.32%,热阻降低27.05%。各影响因素中石墨层厚度对封装结温和热阻影响最大,其次是铜柱直径和铜层厚度。进一步优化后,结温降低了2.1%,热阻降低了3.4%。此封装结构实现了优异的散热性能,为高导热石墨在功率模块热管理中的应用提供参考。     

Thermal Investigation of GaN-Based Laser Diode Package

We investigated thermal behavior of GaN-based laser diode (LD) packages as a function of cooling systems, die attaching materials, chip loading conditions, and optical performances. The electrical thermal transient technique was employed for the thermal measurement of junction temperature and thermal resistance of LD packages. The results demonstrate that the total thermal resistance of LD packages is controlled mainly by the packaging design rather than the chip structure itself. Significant changes in thermal resistance with input current were observed under a natural cooling system because of the sensitive change in the heat transfer coefficient with the change in temperature. Employment of PbSn as a die attachment was more advantageous over the Ag-paste in the thermal behavior of LD packages. The LD package with epi-down structure resulted in the lower thermal resistance compared to one with epi-up structure. A continuous increase in junction temperature was measured after lasing. It was attributed to an increase in the thermal resistance of LD when it took the optical power into an account. Effective input power was decreased by the lasing and led to high thermal resistance values.     

Parameter driven monitoring for a flip-chip LED module under power cycling condition

In this paper, a parameter driven monitoring model is introduced, in which a flip-chip LED module was investigated during a power cycling test. This approach was investigated to develop a monitoring model to describe thermally induced solder fatigue as root cause of flip-chip failure in a power cycling test. As monitoring parameter the thermal resistance of the LED module was used, which was determined by thermal impedance measurements of the whole LED module, as well as for each LED chip itself. Further analyses of the occurring temperature at the LED junction recorded of each chip during the power cycling test were used to generate a prediction model. The evaluation of the temperature change allowed to forecast the number of cycles until failure.     

改善不同环境温度下SiGe HBT热稳定性的技术

提出了发射极非均匀指间距技术以增强多发射极指SiGe HBT在不同环境温度下的热稳定性。通过建立热电反馈模型对采用发射极非均匀指间距技术的SiGe HBT进行热稳定性分析,得到多发射极指上的温度分布。结果表明,与传统的均匀发射极指间距SiGe HBT相比,在相同的环境温度及耗散功率下,采用发射极非均匀指间距技术的SiGe HBT,其最高结温明显降低,热阻显著减小,温度分布更加均匀,有效地提高了多发射极指功率SiGe HBT在不同环境温度下的热稳定性。     

Integration of Simulation and response surface methods for thermal design of multichip modules

This paper presents a mathematical expression of the chip junction temperature in terms of chip spatial location and size for effective thermal characterization of ball grid array (BGA) typed multichip modules (MCMs). It is created through the integration of the finite element (FE) analysis and the response surface methods (RSMs) that introduce an approximation of the chip junction temperature in the form of a global response surface. In place of FE simulations, the global response surface is then used to effectively characterize the thermal performance of MCMs, and facilitate the thermal management and the finding of the optimal thermal design of MCMs. To create a set of response data, a rigorous three-dimensional (3D) FE modeling of the MCM package is first established for thermal analysis. The surface loads of the FE model for the heat conduction problems are described by using existing heat transfer (HT) coefficient correlation models. The validity of the proposed FE modeling is substantiated by both the IR thermography-based thermal characterization (IRTTC) approach and the thermal test die measurement based on joint electron device engineering council (JEDEC) specification under a natural convection environment. The uncertainty of the specific power supply applied in the study and the thermal test die measurement is also analyzed. To demonstrate the proposed methodology, two types of MCM thermal design problems are fulfilled, each of which corresponds to a different chip layout. It turns out that the mathematical expression could not only effectively define the relation of the thermal performance and design parameters but also highlight their combinatorial effect.     

From chip to inverter: Electro-thermal modeling and design for paralleled power devices in high power application

Power loss and thermal stress of semiconductor components are closely related to the reliability of high power inverter. In addition to the inverter electrical parameters, the size of semiconductor is also an important factor in inverter electro-thermal performance. In this paper, an electro-thermal model correlated with chip area and chip paralleled number is built to calculate the power switch loss and junction temperature. Then, the relationship between chips size and inverter loss/thermal behaviors can be established by this model, enabling more flexible in chip design to optimize the inverter efficiency and thermal loading. Finally, the inverter electro-thermal design procedure is established to properly select the chip area and number in a power switch. As a case study, the optimal chip paralleled structure in the high power inverter is estimated and the results are compared under varying inverter output frequency. By selecting the chip area and number in the target region, junction temperature can maintain in the limited range.     

基于倒装焊芯片的功率型LED热特性分析

对LED的导散热理论进行了研究,推导出了倒装焊LED芯片结温与封装材料热传导系数之间的关系。通过分析倒装焊LED的焊球材料、衬底粘结材料和芯片内部热沉材料对芯片结温的影响,表明衬底粘结材料对LED的结温影响最大,并且封装材料热传导系数的变化率与封装结构的传热厚度成反比,与传热面积成正比。该研究为倒装焊LED封装结构和材料的设计提供了理论支持。     

Experimental and numerical investigation into the influence ofprinted circuit board construction on component operating temperature innatural convection

The steady state thermal performance of an isolated SO-8 package is experimentally characterized on five thermal test printed circuit boards (PCBs) and the results compared against corresponding numerical predictions. The study includes the low and high conductivity JEDEC standard, FR4 test PCBs and typical application boards. With each PCB displaying a different internal structure and effective thermal conductivity, this study highlights the sensitivity of component operating temperature to the PCB, provides benchmark data for validating PCB numerical modeling methodologies, and helps one assess the applicability of standard junction-to-ambient thermal resistance (&thetas;_JA) data for design purposes on nonstandard PCBs. Measurements of junction temperature and component-PCB surface temperature distributions were used to identify the most appropriate modeling methodology for both the component and the PCB. Based on these results, a new PCB modeling methodology is proposed that conserves the need for modeling detail without compromising prediction accuracy     

小封装二极管的热阻测试

随着封装体积的减小,半导体分立器件引线的外露部分也越来越小,这给引线温度的测试带来了巨大挑战.以封装外形为SOD-123FL的小电流整流二极管为例,介绍了结到引线的热阻和结到环境的热阻的测试方法.通过测量焊接于引线端部的小尺寸二极管芯片以及被测样品在不同温度下的热敏电压,实现了对小封装器件的引线温度和二极管本身结温的精密测量.     

IGBT junction and coolant temperature estimation by thermal model

The capability of IGBT (Insulated Gate Bipolar Transistor) to handle heat is one of its main limitations of high power application. This paper aims to study an IGBT thermal model under flow cooling condition and estimate the IGBT module junction and coolant temperature. Firstly, this paper studies the IGBT module internal sandwich structure and calculates the thermal resistance and thermal capacitor for each layer using a 1D physical model. Then a Cauer electric model is built for the IGBT module to evaluate the thermal constant time of the model. The liquid cooling method is applied in this project for fast cooling and the thermal parameters are studied and measured since this cooling method involves both solid and liquid. In order to estimate the junction temperature, the sensing temperature from NTC (Negative temperature coefficient) resistor inside the module is used as reference temperature. The equivalent thermal models, also named Foster model, from both junction to NTC and NTC to coolant are built, respectively. With these thermal models, the junction and coolant temperature estimation methods are derived. For the purpose of making the estimation accurate, the thermal coupling effect is carefully studied. Finally, the thermal model is verified by inverter application with current steps sweeping; the estimated temperature is compared with thermal camera measurement result which demonstrates good accuracy of the thermal model. The estimated coolant temperature is also well matched with thermocouple measurement result.