Optimising the location of crossovers in conveyor-based automated material handling systems in semiconductor wafer fabs

This research presents several heuristics to optimise the location of crossovers in a conveyor-based automated material handling system (AMHS) for a semiconductor wafer fabrication facility. The objective is to determine the location of crossovers that minimises the total cost of the expected work-in-process on the conveyor and the cost of installing and operating the AMHS with the crossovers. The proposed heuristics are integrated with a queuing-based analytical model incorporating practical hardware considerations of the AMHS, such as turntables and crossovers. To illustrate the proposed heuristics’ practical application they are applied to SEMATECH's virtual wafer fabrication facility. Experimental results demonstrate that under a wide variety of operating conditions and cost scenarios the local improvement heuristic is able to identify the optimal solution and outperform other commonly used heuristics for layout design such as genetic algorithms.     

AMHS capacity determination model for wafer fabrication based on production performance optimization

Automatic material handling system (AMHS) is becoming more important in 300?mm wafer fabrication factories (fab). Effective and efficient design and control of AMHS has become more critical particularly in capacity planning. The major concept of the AMHS capacity determination model is to maintain the originally designed optimal production throughput or cycle time of products. In order to maintain fab’s throughput or cycle time of products, WIP (work in process) portfolio of the constraint or the fastest workstation should be kept. Based on this concept, a GI/G/m queuing model based on FCFS (First-come-first-serve) dispatching rule of AMHS is applied to determine the required number of vehicles. Basically, products should be transported to the specific workstation (constraint or fastest workstation) before the workstation finishes the existing process; therefore, sufficient WIP in front of this specific workstation should be kept. Under this condition, the probability that transportation time exceeds product processing time under a certain transportation capacity level can be calculated by the proposed model. Hence, we can get the required capacity of AMHS to achieve the probability target set in advance. Due to the capacity of AMHS can be set according to the acceptable probability of non-exceeding the processing time of the constraint or fastest workstation, the level of WIP in front of this workstation can be kept. It also can be ensured that AMHS will not affect the production performance as well as keep the reasonable investment level.     

Optimal vehicle allocation for an Automated Materials Handling System using simulation optimisation

The Automated Materials Handling System (AMHS) in the semiconductor industry plays a vital role in reducing wafer cycle times and enhancing fabrication facility (fab) productivity. Due to the complexity of the manufacturing process and the stochasticity introduced by the inherent variability of processing times, the vehicle allocation for the AMHS is a challenging task, especially in 300?mm?wafer fabs where the AMHS comprises both the interbay and intrabay systems to perform the timely deliveries. This paper studied the vehicle allocation problem in a typical 300?mm?wafer fab. We formulated it as a simulation optimisation problem and proposed a conceptual framework to handle the problem. A discrete event simulation model was developed to characterise the AMHS, and the technique of simulation optimisation was applied to obtain the optimal vehicle allocation for both the interbay and intrabay systems. To demonstrate the feasibility and advantages of the simulation optimisation approach, a photobay example was used to compare the solution derived from the analytical model and simulation optimisation model. Finally, an empirical problem based on real data was conducted to show the viability of the proposed framework in practice.     

Simulation analysis of dispatching rules for an automated interbay material handling system in wafer fab

Here, the performance evaluation of a double-loop interbay automated material handling system (AMHS) in wafer fab was analysed by considering the effects of the dispatching rules. Discrete event simulation models based on SIMPLE++ were developed to implement the heuristic dispatching rules in such an AMHS system with a zone control scheme to avoid vehicle collision. The layout of an interbay system is a combination configuration in which the hallway contains double loops and the vehicles have double capacity. The results show that the dispatching rule has a significant impact on average transport time, waiting time, throughput and vehicle utilization. The combination of the shortest distance with nearest vehicle and the first encounter first served rule outperformed the other rules. Furthermore, the relationship between vehicle number and material flow rate by experimenting with a simulation model was investigated. The optimum combination of these two factors can be obtained by response surface methodology.     

Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities

In semiconductor wafer fabrication facilities, order-lot pegging is the process of assigning wafer lots to orders and meeting the due dates of orders is considered one of the most important operational issues. In many cases of order-lot pegging, some orders cannot be fulfilled with the current wafers in the lots being processed, necessitating the release of additional new wafer lots into the wafer fabrication facility. In this paper, we propose a simultaneous decision model for order-lot pegging and wafer release planning in semiconductor wafer fabrication facilities, and develop a Lagrangian heuristic for solving the model. The results of computational experiments conducted using randomly generated problem instances that mimic actual field data from a Korea semiconductor wafer fabrication facility indicate that the performance of the Lagrangian heuristic is superior to that of a practical greedy algorithm for practical-sized problem instances. The results also point to how sensitivity analysis can be used to answer important managerial questions for effective management of the semiconductor wafer fabrication process.     

The infrastructure of the timed EOPNs-based multiple-objective real-time scheduling system for 300 mm wafer fab

Modern semiconductor wafer fabrication systems are changing from 200?mm to 300?mm wafer processing, and with the dual promises of more chips per wafer and economy of scale, leading semiconductor manufacturers are attracted to developing and implementing 300?mm wafer fabs. However, in today's dynamic and competitive global market, a successful semiconductor manufacturer has to excel in multiple performance indices, such as manufacturing cycle time and on-time delivery, and simultaneously optimize these objectives to reach the best-compromised system achievement. To cope with this challenge, in this paper, the infrastructure of a timed EOPNs-based multiple-objective real-time scheduling system (MRSS) is proposed to tackle complex 300?mm wafer fabs. Four specific performance objectives pursued by contemporary semiconductor manufacturers are integrated into a priority-ranking algorithm, which can serve as the initial scheduling guidance, and then all wafer lots will be dynamically dispatched by the real-time state-dependent dispatching system. This dispatching control system is timed EOPN-based and adopts a heterarchical organization that leads to a better real-time performance and adaptability. As the foundation of real-time schedule, the timed EOPNs modelling approach is expounded in detail, and the prototype of the MRSS simulation system is also provided.     

A cost-effective wafer-level reliability test system for integrated circuit makers

Wafer-level reliability (WLR) testing receives much attention and becomes a major tool for process reliability qualification and in-line monitoring because WLR can provide real-time results for timely improvements. This in-situ test capability is greatly attributed to an automatic parametric tester for sample handling and data collection/analysis. This paper presents a cost-effective WLR test system for a semiconductor maker (an IDM as well as a foundry). The proposed system consists of flexible and extensible algorithm generation, which helps realize low-cost WLR solutions. The key features of our proposed system include cost-effective instrumentation (i.e., an Agilent 4156C parameter analyzer, a semi-auto, and thermal CASCADE 12751 wafer prober, a pulse generator, and a switching matrix) and the software for interface control and data analysis. Compared with the corresponding automatic test equipment (ATE), our system is capable of measuring electrical characteristics with higher accuracy and a wider temperature range. This leads to significant cost saving, much enhanced tool utilization, and improved flexibility. Its great extensibility is especially important for a wafer foundry, which often suffers test capacity shortage when numerous verifications and qualifications are to be done.     

Effectiveness of vehicle reassignment in a large-scale overhead hoist transport system

This paper proposes an efficient vehicle reassignment dispatching rule and demonstrates the effectiveness of the rule using an overhead hoist transport (OHT) system for a semiconductor fabrication line. The OHT system has more than 150 OHT vehicles and its target vehicle utilization level is 70%. It allows direct delivery such that an inter-bay wafer movement can be accomplished by a single vehicle. Simulation analysis is used to compare the proposed rule with the shortest travel distance first (STDF) rule and existing reassignment-based rules. While STDF rule requires 170 vehicles for the target utilization level, the proposed vehicle reassignment rule requires only 161 vehicles. At the same time, the lead time and the variance of the lead time have been significantly reduced. The proposed rule also improves system performance compared to existing reassignment-based rules.     

Development of a real-time multi-objective scheduler for a semiconductor fabrication system

Semiconductor wafer fabrication involves possibly one of the most complex manufacturing processes ever used. This causes a number of decision problems. A successful system control strategy would assign appropriate decision rules for decision variables. Therefore, the goal of this study is to develop a scheduler for the selection of decision rules for decision variables in order to obtain the desired performance measures given by a user at the end of a certain production interval. In this proposed methodology, a system control strategy based on a simulation technique and a competitive neural network is suggested. A simulation experiment was conducted to collect the data containing the relationship between the change of decision rule set and current system status and the performance measures in the dynamic nature of semiconductor manufacturing fabrication. Then, a competitive neural network was applied to obtain the scheduling knowledge from the collected data. The results of the study indicate that applying this methodology to obtaining a control strategy is an effective method considering the complexity of semiconductor wafer fabrication systems.     

A discrete spatial model for wafer yield prediction

Yield analysis is one of the key concerns in the fabrication of semiconductor wafers. An effective yield analysis model will contribute to production planning and control, cost reductions and the enhanced competitiveness of enterprises. In this article, we propose a novel discrete spatial model based on defect data on wafer maps for analyzing and predicting wafer yields at different chip locations. More specifically, based on a Bayesian framework, we propose a hierarchical generalized linear mixed model, which incorporates both global trends and spatially correlated effects to characterize wafer yields with clustered defects. Both real and simulated data are used to validate the performance of the proposed model. The experimental results show that the newly proposed model offers an improved fit to spatially correlated wafer map data.     

Modelling,control and simulation of an IC wafer fabrication system: A generalized stochastic coloured timed Petri Net approach

This study presents a generalized stochastic coloured timed Petri net(GSCTPN) to model an IC wafer fabrication system. According to the GSCTPN, it models the dynamic behaviours of the IC fabrication system, such as loading, reentrant processing, unloading and machine failure. Furthermore, modular and synthesis techniques are used to construct a large and complex system model. The two major sub-models are the Process-Flow Model and the Transportation Model. The Transportation Model incorporates a simple motion-planning rule and a collision avoidance strategy to solve the variable speed and traffic jam problems of vehicles. This work also describes a simulation based performance analysis and schedule adjustment. To demonstrate the promise of the proposed work, this study makes actual Taiwanese IC wafer fabrication systems the target plant layout for implementation.     

Selection of dispatching rules on multiple dispatching decision points in real-time scheduling of a semiconductor wafer fabrication system

Semiconductor wafer fabrication involves one of the most complex manufacturing processes ever used. To control such complex systems, it is a challenge to determine appropriate dispatching strategies under various system conditions. Dispatching strategies are classified into two categories: a vehicle-initiated dispatching policy and a machine-initiated dispatching policy. Both policies are important to improve the system performance, especially for the real time control of the system. However, there has been little research focusing on combining them under various situations for the semiconductor manufacturing system. In addition, it is shown that no single dispatching strategy consistently dominates others in all situations. Therefore, the goal of this study is to develop a scheduler for selection of dispatching rules for dispatching decision variables in order to obtain the desired performance measures given by a user for each production interval. For the proposed methodology, simulation and competitive neural network approaches are used. The results of the study indicate that applying our methodology to obtaining a dispatching strategy is an effective method considering the complexity of semiconductor wafer fabrication systems.     

Capacity planning with sequential two-level time constraints in the back-end process of wafer fabrication

A time constraint is a queue-time boundary that is set between particular sequential operations to ensure final product yield. These time boundaries, called ‘sequential time constraints’, can be found in a series of operations on the back-end of wafer fabrication. Wafers exceeding the time constraints are traced through the fabrication process, but generally pass through the remaining processes. Nonetheless, it is a waste of capacity to continue processing wafers with unacceptable yield. Unfortunately, these unacceptable wafers cannot be identified before the wafer acceptance test using the current control policy. This work proposes a control rule for two-level time constraints with capacity planning methodology under this rule. Wafers exceeding the lower time constraints will be treated as normal wafers; however, once wafers exceed the upper time constraint, they will be scrapped immediately. In the capacity planning model, a GI/G/m queuing network is applied to determine the required number of machines. By pre-setting target yields, the rates of wafers being marked or scrapped can be controlled. Furthermore, a novel scheme–regarding machine failures as irregular customers–is introduced to describe the effect of service interruptions. The results show that the proposed control rule and capacity planning model can more effectively resolve the issues of sequential time constraints. Moreover, the results of the analysis indicate that the current capacity expansion policy of the semiconductor industry should be re-examined.     

Estimating the sustainable capacity of semiconductor fab workstations

The cost of a semiconductor wafer fabrication facility (i.e. ‘fab’) may be as much as five or more billion US dollars. As such it is essential to determine the capacity (e.g. in terms of ‘wafer starts per week’) of such facilities. An accurate estimate of capacity – under real world conditions – is, however, difficult to achieve. Furthermore, the method for the computation of the capacity of a semiconductor fab is significantly different from that for the capacity of workstations in more conventional, less complex factories. This is due in part to the reentrant nature of the workstations (a.k.a. ‘toolsets’) that comprise a fab's production line as well as the ubiquitous employment of operation-to-machine dedications (a.k.a. layer-to-tool qualifications) – plus the need to consider multiple products employing, perhaps, a different sequence of processing steps. In this article, the matter of workstation capacity, in general, and semiconductor fabs, in particular, is examined. A means to quickly and effectively determine the maximum theoretical capacity of a workstation is developed and illustrated – followed by a way in which the more practical maximum sustainable capacity may be estimated.     

A due-date based production control policy using WIP balance for implementation in semiconductor fabrications

Production control policies are critical in the re-entrant processes of semiconductor fabrication. Manufacturing control policies such as input dispatching rules, CONWIP, and optimization-based rules have been implemented according to the managerial objectives of the wafer fabrication line. When few semiconductor wafer fabrication facilities were available, and the semiconductor industry was a seller's market, fabrications were operated to achieve both a high rate of production and high utilization of equipment. With the availability of more fabrications and the gradual shift to a buyer's market, customer satisfaction became a major measure of performance in semiconductor manufacturing. In this paper, due-date based production control policies for semiconductor fabrications are suggested, and their performances evaluated. Target balance (TB) optimization models using production target, due-dates, and WIP (work-in-process) are presented. The evaluation result shows that the TB models perform better than the ones cited in the literature.     

Effective overhead hoist transport dispatching based on the Hungarian algorithm for a large semiconductor FAB

This paper considers the vehicle dispatching problem in large-scale overhead hoist transport (OHT) systems of semiconductor fabrication lines. We propose a Hungarian algorithm based OHT reassignment approach named HABOR. HABOR attempts to take advantage of simultaneous vehicle reassignment based on up-to-date system status using the formulation of the assignment problem. The effectiveness of HABOR is demonstrated using a sample OHT system of a semiconductor fabrication line with more than 130 vehicles, where the flow path of the line allows direct delivery so that an inter-bay wafer movement can be accomplished by a single vehicle without an intermediate storage step at a stocker. HABOR compares favorably with the shortest travel distance first rule and with the reassignment-based rule recently proposed by the authors.     

Combined scheduling algorithm for re-entrant batch-processing machines in semiconductor wafer manufacturing

In this paper, a new combined scheduling algorithm is proposed to address the problem of minimising total weighted tardiness on re-entrant batch-processing machines (RBPMs) with incompatible job families in the semiconductor wafer fabrication system (SWFS). The general combined scheduling algorithm forms batches according to parameters from the real-time scheduling simulation platform (ReS²), and then sequences batches through slack-based mixed integer linear programming model (S-MILP), which is defined as batch-oriented combined scheduling algorithm. The new combined scheduling algorithm obtains families’ parameters from ReS² and then sequences these families through modified S-MILP, which is defined as family-oriented combined scheduling algorithm. With rolling horizon control strategy, two combined scheduling algorithms can update RBPMs scheduling continually. The experiments are implemented on ReS² of SWFS and ILOG CPLEX, respectively. The results demonstrate the effectiveness of our proposed methods.     

Multiagent-based modeling for re-entrant manufacturing system

Re-entrant flow manufacturing system is a typical mix of different process types, sequence-dependent setup times, very expensive equipment, and re-entrant flows. A multiagent-based modeling technology for re-entrant manufacturing system was addressed. The model of Agent-based Colored Timed Petri-Net (ACTPN) is constructed, which consists of the material flow net model and the interactive protocol model. In the material flow net, the interior behavior of machine agent was encapsulated and it was separated into the system layer, machine group layer and machine agent layer to form a hierarchical multiagent-based model, which reduced the complexity and improved the reusability of the model. In the view of modeling methodology of the interactive protocol net, the transforming rule from Agent Unified Modeling Language (AUML) to ACTPN was given so as to map the AUML model to ACTPN model. In the view of the analysis method of the interactive protocol net, it was integrated with a reachability graph to check the liveness and bound properties of interactive protocol model. A distributed discrete event simulation platform to evaluate the performance of the multiagent-based re-entrant manufacturing system was built. An illustrative example of a 6-inch semiconductor fabrication line in Shanghai demonstrates the effectiveness of the approach proposed.     

An integrated scheduling and material-handling approach for complex job shops: a computational study

We suggest an extension of the shifting bottleneck heuristic for complex job shops that takes the operations of automated material-handling systems (AMHS) into account. The heuristic is used within a rolling horizon approach. The job-shop environment contains parallel batching machines, machines with sequence-dependent setup times, and re-entrant process flows. Jobs are transported by an AMHS. Semiconductor wafer fabrication facilities (wafer fabs) are typical examples for manufacturing systems with these characteristics. Our primary performance measure is total weighted tardiness (TWT). The shifting bottleneck heuristic (SBH) uses a disjunctive graph to decompose the overall scheduling problem into scheduling problems for single machine groups and for transport operations. The scheduling algorithms for these scheduling problems are called subproblem solution procedures (SSPs). We consider SSPs based on dispatching rules. In this paper, we are also interested in how much we can gain in terms of TWT if we apply more sophisticated SSPs for scheduling the transport operations. We suggest a Variable Neighbourhood Search (VNS) based SSP for this situation. We conduct simulation experiments in a dynamic job-shop environment in order to assess the performance of the suggested algorithms. The integrated SBH outperforms common dispatching rules in many situations. Using near to optimal SSPs leads to improved results compared with dispatching based SSPs for the transport operations.     

Shift scheduling for steppers in the semiconductor wafer fabrication process

In this paper, an approach is proposed for scheduling stepper machines that are acting as bottleneck machines in the semiconductor wafer fabrication process. We consider the problem of scheduling the steppers for an 8 hour shift, determining which types of wafer lots to work on each machine. The scheduling objective is to find the optimal stepper allocations such that the schedule meets target production quantities that have been derived from the given target Work-In-Process (WIP) levels. A Mixed Integer Programming (MIP) model is formulated, and three heuristic approaches are proposed and tested to approximately solve the M1P model. Numerical tests show that one of the proposed heuristics using linear programming relaxation of MIP generates, on average, schedules within 5° of the optimum values.