1～400MHz,1～900MHz混合集成系列放大器

采用厚薄膜混合集成电路工艺,研制了1～400MHz,1～900MHz系列混合集成放大器。由于采用了负反馈电路,放大器具有优良的增益平坦特性、温度特性和稳定性。良好的匹配性能可使放大器多级级联。     

兼顾低噪声与低失真 TI全差动放大器驱动100MHz ADC

更多的产品需要更高的带宽、处理速度以及分辨率催生了高速放大器市场的蓬勃发展.据Databeans估计数据显示,2003年到2009年全球高速放大器市场的年复合增长率(CAGR)高达13.4%,具有很大的发展潜力.专精模拟技术的TI(德州仪器)最近又推出可实现数据转换器性能的低噪声与低失真全差动放大器,其性能可满足高速模数转换器(ADC)频率高达100MHz.     

200MHz宽带放大电路的设计

宽带通信技术的不断发展,使其对宽带放大的要求也越来越高,其中设计一款宽带放大器是一项关键的技术,能在满足基本要求的基础上进一步提高系统的性能是设计的关键。文章对电流反馈型宽带放大原理进行研究,对宽带放大器的关键特性参数进行分析,并利用TI的OPA691芯片搭建了超过200MHz(3db带宽)的实测放大电路,验证了该模块具有良好的线性度和较强的抗干扰性。     

一种新型900MHz CMOS低噪声放大器的设计

对两种低噪声放大器(LNA)的构架进行了比较,详细推导了共源LNA的噪声系数与输入晶体管栅宽的关系及优化方法,设计了一种采用0.6 μ m标准CMOS工艺,工作于900MHz的新型差分低噪声放大器.在900MHz时,噪声系数为1.5 dB的情况下可提供22.5 dB的功率增益,-3dB带宽为1 50MHz,S11达到-38dB,消耗的电流为5mA.     

放大器均衡插片的550 MHz升级改造

通过对放大器均衡插片电路图的分析讨论,提出了将300 MHz的均衡插片升级改造为550 MHz的方法.     

225MHz～512MHz宽带功放设计与仿真

根据宽带功放的设计原理,采用平衡式结构,负反馈技术,稳定化技术,传输线变压器以及微带混合匹配电路设计出了一款宽带功率放大器。用ADS对其进行优化仿真,通过分析仿真结果,可以看出在225 MHz～512 MHz频段内,放大器功率增益可达到23 dB,增益平坦度小于1.1 dB,理想情况下输入输出驻波比达到1∶1,并具有良好的稳定性。     

一种700 MHz频段的高线性驱动放大器MMIC

采用GaAsPHEMT工艺,设计了一种700 MHz频段的高线性驱动放大器MMIC.该放大器内部集成了带通复合匹配网络结构的宽带输入匹配电路,通过两种幅频特性相反的匹配网络进行组合,有效地拓展了应用带宽,提高了线性度和增益平坦度.放大电路采用两级放大结构,保证增益指标,引入稳定性设计以保证放大器工作的稳定性.偏置电路采用带负反馈系统的有源镜像结构,提高了驱动能力,使电路更加稳定.该放大器集成输出检波器,采用二极管检波器结构实现功率检波,具有结构简单、占用芯片面积小的优点.该放大器典型频点700 MHz处的输出三阶交调点为42.6 dBm,1 dB压缩点输出功率为27.6 dBm.通过调整片外输出匹配电路可满足700 MHz及其他频段的应用需求.     

一种10 MHz带宽70 dB动态范围连续时间Sigma-Delta调制器

介绍了4阶反馈型连续时间Sigma-Delta调制器从顶层到底层的详细设计过程。采用数字置乱技术,降低失配对输出杂散的影响,使失配产生的谐波被转换为噪声,并被移出通带外。将谐振腔内嵌于调制器环路中,以改善带内信噪比。采用三级前馈型放大器,调制器具备更高的能效。该调制器基于65 nm CMOS工艺设计并流片。测试结果表明,在时钟频率为614.4 MHz、信号带宽为10 MHz时,调制器的SNDR为70.1 dB,动态范围达70 dB。功耗为77 mW。该调制器芯片的内核面积为4.50 mm²。     

基于MAX7033的315MHz/433 MHz ASK超外差式接收电路设计

所设计的315 MHz/433 MHz ASK超外差式接收机电路采用MAX7033高集成度、低功耗CMOS、超外差式幅移键控(ASK)接收机,接收频率范围为300MHz～450 MHz,射频信号输入范围为-114 dBm～0 dBm,数据速率可达33 kb/s曼彻斯特码率(66 kb/s NRZ).介绍了MAX7033的主要技术性能、内部结构、工作原理和应用电路.     

一种低功耗12位30 MHz流水线A/D转换器

设计了一种12位30 MHz 1.8 V流水线结构A/D转换器,该A/D转换器采用相邻级运算放大器共享技术和逐级电容缩减技术,其优点是可以大大减小芯片的功耗和面积.电路采用级联一个高性能前置采样保持单元和五个运放共享的1.5位/级MDAC,并采用栅压自举开关和动态比较器来降低功耗.结果显示,该ADC能够工作在欠采样情况下,有效输入带宽达到50 MHz.在输入频率达到奈奎斯特频率范围内,整个ADC的有效位数始终高于10.4位.电路使用TSMC 0.18 μm 1P6M CMOS工艺,在30 MHz全速采样频率下,电路功耗仅为68 mW.     

800MHz800W固态脉冲功放组件

介绍一种大功率固态脉冲功放组件。该组件在 80 0 MHz中心频率处 ,峰值输出功率大于80 0 W,带宽 50 MHz,脉冲宽度 0 .8μs,脉冲工作比 1%。组件性能稳定 ,已用于气象雷达。     

A 500-600 MHz GaN power amplifier with RC-LC stability network

A 500-600 MHz high-efficiency, high-power GaN power amplifier is designed and realized on the basis of the push-pull structure. The RC-LC stability network is proposed and applied to the power amplifier circuit for the first time. The RC-LC stability network can significantly reduce the high gain out the band, which eliminates the instability of the power amplifier circuit. The developed power amplifier exhibits 58.5 dBm (700 W) output power with a 17 dB gain and 85% PAE at 500-600 MHz, 300 μs, 20% duty cycle. It has the highest PAE in P-band among the products at home and abroad.     

Cryogenic noise performance of HEMTs and MESFETs between 300 and700 MHz

The authors present the noise performance of amplifiers using HEMTs and MESFETs at room temperature and cryogenic temperatures, in the frequency range 300-700 MHz. Results demonstrate that these microwave devices can be applied at frequencies down to at least 300 MHz, giving amplifier noise temperatures below 2 K at 20 K ambient temperature     

An Inductorless 300 MHz Wideband CMOS Power Amplifier

The power amplifier tends to be one of the most demanding parts to fully integrate when building an entire radio on a CMOS chip. In this paper the design of a fully integrated RF power amplifier without inductors is described. As inductors in CMOS technology are associated with various problems, it is interesting to examine what performance can be achieved without them. An amplifier with an operating band from 60 MHz to 300 MHz (–3 dB) is built in 0.8 m CMOS. A 3 V supply is used. The measured midband power gain is 30 dB with 50 resistive source and load impedance. As linearity is important for many modern modulation schemes, the amplifier is designed to be as linear as possible. The measured third order intercept point is 23 dBm and the 1 dB compression point is 10 dBm, both referred to the output. The output is single ended to avoid an off-chip differential to single ended transformer.     

一种10位50MHz流水线模数转换器的设计

采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。     

Performance of different simple linearizing techniques in SiGe LNA at 1900 MHz

Five different linearizing methods were implemented to improve the linearity of a low noise amplifier (LNA). Obtaining a very good performance concerning output and input third-order intercept point without significant degradation of the noise figure. Moreover, high 1 dB-gain compression point was succeeded, obtaining a very high linear amplifier operating at 1900 MHz and biased with 2.4 V and 10 mA of collector current.     

低功耗10位100MHz流水线A/D转换器设计

介绍了一个10位100 MHz,1.8 V的流水线结构模/数转换器（ADC）,该ADC运用相邻级运算放大器共享技术和逐级电容缩减技术,可以大大减小芯片的功耗和面积。电路采用级联1个高性能前置采样保持单元和4个运放共享的1.5位/级MDAC,并采用栅压自举开关和动态比较器来缩减功耗。结果显示,在输入频率达到奈奎斯特频率范围内,整个ADC的有效位数始终高于9位。电路使用TSMC 0.18μm 1P6 M CMOS工艺,在100 MHz的采样频率下,功耗仅为45 mW。     

A BiCMOS wideband operational amplifier with 900 MHz gain-bandwidth and 90 dB DC gain

A fully differential operational amplifier has been designed and fabricated for a novel high resolution and high frequency analog-to-digital converter(>12-bit). The amplifier mainly consists of folded cascode structure with current source as output loads and common-mode feedback circuits. The technique of feedforward compensation is used in order to improve the settling time and gain bandwidth (GBW) of this amplifier. This amplifier is integrated in 0.8 mm BiCMOS process with an active die area of 0.1 mm². The DC gain of this amplifier is 90 dB. The GBW and phase margin of this amplifier is 900 MHz and 47°, respectively. The power dissipation is minimized by using BiCMOS technology and is about 25 mW for 2 pF load capacitance. This level of performance is competitive with CMOS and BiCMOS operational amplifier circuits previously reported by nearly two orders of magnitude.Ecole Polytechnique of the University of Montreal     

High-gain wideband error amplifier topology for DC-DC buck converter switching at 20 MHz

A wideband error amplifier topology with increased DC-gain and reduced quiescent current consumption is presented. The reduction in quiescent current consumption is achieved by lowering the output stage current, which helps to increase the output impedance and hence the overall DC-gain of the amplifier. Simulation results show that the proposed topology has 60 dB DC gain and 540 MHz unity gain bandwidth with 450 muA quiescent current consumption. The experimental result of the loop-gain of a high-frequency (20 MHz) DC-DC buck converter that utilises the proposed topology also confirms the simulation results.