InGaAs/InP DHBTs with 120-nm collector having simultaneously high f/sub /spl tau//, f/sub max//spl ges/450 GHz

InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction.     

InGaAs-InP mesa DHBTs with simultaneously high f/sub /spl tau// and f/sub max/ and low C/sub cb//I/sub c/ ratio

We report an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT), fabricated using a conventional triple mesa structure, exhibiting a 370-GHz f/sub /spl tau// and 459-GHz f/sub max/, which is to our knowledge the highest f/sub /spl tau// reported for a mesa InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The collector semiconductor was undercut to reduce the base-collector capacitance, producing a C/sub cb//I/sub c/ ratio of 0.28 ps/V at V/sub cb/=0.5 V. The V/sub BR,CEO/ is 5.6 V and the devices fail thermally only at >18 mW//spl mu/m/sup 2/, allowing dc bias from J/sub e/=4.8 mA//spl mu/m/sup 2/ at V/sub ce/=3.9 V to J/sub e/=12.5 mA//spl mu/m/sup 2/ at V/sub ce/=1.5 V. The device employs a 30 nm carbon-doped InGaAs base with graded base doping, and an InGaAs-InAlAs superlattice grade in the base-collector junction that contributes to a total depleted collector thickness of 150 nm.     

A fault-tolerant 256K RAM fabricated with molybdenum-polysilicon technology

Describes a 256K molybdenum-polysilicon (Mo-poly) gate dynamic MOS RAM using a single transistor cell. Circuit technologies, including a capacitive-coupled sense-refresh amplifier and a redundant circuitry, enable the achievement of high performance in combination with Mo-poly technology. Electron-beam direct writing and dry etching technologies are fully utilized to make 1 /spl mu/m accurate patterns. The 256K word/spl times/1 bit device is fabricated on a 5.83 mm/spl times/5.90 mm chip. Cell size is 8.05 /spl mu/m/spl times/8.60 /spl mu/m. The additional 4K spare cells and the associated circuits, in which newly developed electrically programmable elements are used, occupy less than 10 percent of the whole chip area. The measured access time is 160 ns under V/SUB DD/=5 V condition.     

GaInAsSb/GaSb pn photodiodes for detection to 2.4 mu m

Ga/sub 0.77/In/sub 0.23/As/sub 0.20/Sb/sub 0.80//GaSb pn heterojunction photodiodes have been prepared by liquid phase epitaxy. They exhibit a long-wavelength threshold of 2.4 mu m. The room-temperature dark current at V=-0.5 V is 3 mu A (10 mA/cm/sup 2/) and the external quantum efficiency is around 40% in the wavelength range 1.75-2.25 mu m. The estimated detectivity D* at 2.2 mu m is 8.8*10/sup 9/ cm Hz/sup 1/2/ W/sup -1/.<>     

A 160-GHz f/sub T/ and 140-GHz f/sub MAX/ submicrometer InP DHBT in MBE regrown-emitter technology

We report a 0.7/spl times/8 /spl mu/m/sup 2/ InAlAs-InGaAs-InP double heterojunction bipolar transistor, fabricated in a molecular-beam epitaxy (MBE) regrown-emitter technology, exhibiting 160 GHz f/sub T/ and 140 GHz f/sub MAX/. These initial results are the first known RF results for a nonselective regrown-emitter heterojunction bipolar transistor, and the fastest ever reported using a regrown base-emitter heterojunction. The maximum current density is J/sub E/=8/spl times/10/sup 5/ A/cm/sup 2/ and the collector breakdown voltage V/sub CEO/ is 6 V for a 1500-/spl Aring/ collector. In this technology, the dimension of base-emitter junction has been scaled to an area as low as 0.3/spl times/4 /spl mu/m/sup 2/ while a larger-area extrinsic emitter maintains lower emitter access resistance. Furthermore, the application of a refractory metal (Ti-W) base contact beneath the extrinsic emitter regrowth achieves a fully self-aligned device topology.     

High-responsivity high-gain In/sub 0.53/Ga/sub 0.47/As-InP quantum-well infrared photodetectors grown using metal-organic vapor phase epitaxy

We report the growth and fabrication of bound-to-bound In/sub 0.53/Ga/sub 0.47/As-InP quantum-well infrared photodetectors using metal-organic vapor phase epitaxy. These detectors have a peak detection wavelength of 8.5 /spl mu/m. The peak responsivities are extremely large with R/sub pk/=6.9 A/W at bias voltage V/sub b/=3.4 V and temperature T=10 K. These large responsivities arise from large detector gain that was found to be g/sub n/=82 at V/sub b/=3.8 V from dark current noise measurements at T=77 K and g/sub p/=18.4 at V/sub b/=3.4 V from photoresponse data at T=10 K. The background-limited temperature with F/1.2 optics is T/sub BLIP/=65 K for 0相似文献   

A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads

A 25-ns 4-Mbit CMOS SRAM with 512 K word*8-bit organization has been developed. The RAM was fabricated using a 0.5- mu m double-poly and double-aluminum CMOS technology and was assembled in a 32-pin 400-mil DIP. A small cell size of 3.6*5.875 mu m/sup 2/ and a chip size of 7.46*17.41 mm/sup 2/ were obtained. A fast address access time of 25 ns with a single 3.3-V supply voltage has been achieved using the newly developed dynamic bit-line load (DBL) circuit scheme incorporated with an address transition detector (ATD), divided word-line structure (DWL), three-stage sense amplifier, and low-noise output circuit approach. A low operating current of 46 mA at 40 MHz and low standby currents of 70 mu A (TTL) and 5 mu A (CMOS) were also attained.<>     

High breakdown voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode pHEMT with field-plate technology

A high breakdown voltage and a high turn-on voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode (E-mode) pseudomorphic HEMT (pHEMTs) with field-plate (FP) process is reported for the first time. Between gate and drain terminal, the transistor has a FP metal of 1 /spl mu/m, which is connected to a source terminal. The fabricated 0.5/spl times/150 /spl mu/m/sup 2/ device can be operated with gate voltage up to 1.6 V owing to its high Schottky turn-on voltage (V/sub ON/=0.85 V), which corresponds to a high drain-to-source current (I/sub ds/) of 420 mA/mm when drain-to-source voltage (V/sub ds/) is 3.5 V. By adopting the FP technology and large barrier height (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P layer design, the device achieved a high breakdown voltage of -47 V. The measured maximum transconductance, current gain cutoff frequency and maximum oscillation frequency are 370 mS/mm, 22 GHz , and 85 GHz, respectively. Under 5.2-GHz operation, a 15.2 dBm (220 mW/mm) and a 17.8 dBm (405 mW/mm) saturated output power can be achieved when drain voltage are 3.5 and 20 V. These characteristics demonstrate that the field-plated (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P E-mode pHEMTs have great potential for microwave power device applications.     

Low dark current quasi-Schottky barrier MSM-photodiode structures on n-Ga/sub 0.47/In/sub 0.53/As with p/sup +/-Ga/sub 0.47/In/sub 0.53/As cap layer

The p/sup +/-cap layer was used to fabricate a metal-semiconductor-metal (MSM) interdigitated photodetector on Ga/sub 0.47/In/sub 0.53/As. The measured barrier height was Phi /sub Bn=/0.52 V, the ideality factor n=1.1 and average dark current density 2 mA/cm/sup 2/. A rise time of 45 ps at lambda =1.3 mu m under 2 V bias was measured for an MSM photodiode with 3 mu m finger width and finger gaps and an active area of 100*100 mu m/sup 2/.<>     

Application of high-quality SiO/sub 2/ grown by multipolar ECR source to Si/SiGe MISFET

A 5 nm-thick SiO/sub 2/ gate was grown on an Si (p/sup +/)/Si/sub 0.8/Ge/sub 0.2/ modulation-doped heterostructure at 26 degrees C with an oxygen plasma generated by a multipolar electron cyclotron resonance source. The ultrathin oxide has breakdown field >12 MV/cm and fixed charge density approximately 3*10/sup 16/ cm/sup -2/. Leakage current as low as 1 mu A was obtained with the gate biased at 4 V. The MISFET with 0.25*25 mu m/sup 2/ gate shows maximum drain current of 41.6 mA/mm and peak transconductance of 21 mS/mm.<>     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

Fabrication of V-grooved inner stripe GaAs-AlGaAs quantum-wire lasers

V-grooved inner stripe (VIS) GaAs-AlGaAs quantum-wire (QWR) lasers were successfully fabricated by, combining two-step metalorganic chemical vapor deposition (MOCVD) growth with a wet-etching technique. In order to achieve low threshold current density and high reliability, a conductive stripe width (W), a thickness (t/sub p-CBL/), and a doping concentration (n/sub p-CBL/) of the p-GaAs current-blocking layer (CBL) were determined to be W=1.2 /spl mu/m, t/sub p-CBL/=2 /spl mu/m, and n/sub p-CBL/=1/spl times/10/sup 18/ cm/sup -3/. The leakage currents passing through the CBL were also estimated using a modified P-SPICE. Thus far, a threshold current of 45 mA and an output power of 4 mW at 51 mA have been achieved under room-temperature pulsed operation for some devices with uncoated facets.     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop

A 14-GHz 256/257 dual-modulus prescaler is implemented using secondary feedback in the synchronous 4/5 divider on a 0.18-/spl mu/m foundry CMOS process. The dual-modulus scheme utilizes a 4/5 synchronous counter which adopts a traditional MOS current mode logic clocked D flip-flop. The secondary feedback paths limit signal swing to achieve high-speed operation. The maximum operating frequency of the prescaler is 14 GHz at V/sub DD/=1.8 V. Utilizing the prescaler, a 10.4-GHz monolithic phase-locked loop (PLL) is demonstrated. The voltage-controlled oscillator (VCO) operates between 9.7-10.4 GHz. The tuning range of the VCO is 690 MHz. The phase noise of the PLL and VCO at a 3-MHz offset with I/sub vco/=4.9 mA is -117 and -119 dBc/Hz, respectively. At the current consumption of I/sub vco/=8.1 mA, the phase noise is -122 and -122 dBc/Hz, respectively. The PLL output phase noise at a 50-kHz offset is -80 dBc/Hz. The PLL consumes /spl sim/31 mA at V/sub DD/=1.8 V.     

Graded base type-II InP/GaAsSb DHBT with f/sub T/=475 GHz

The first demonstration of a type-II InP/GaAsSb double heterojunction bipolar transistor (DHBT) with a compositionally graded InGaAsSb to GaAsSb base layer is presented. A device with a 0.4/spl times/6 /spl mu/m/sup 2/ emitter dimensions achieves peak f/sub T/ of 475 GHz (f/sub MAX/=265 GHz) with current density at peak f/sub T/ exceeding 12 mA//spl mu/m/sup 2/. The structure consists of a 25-nm InGaAsSb/GaAsSb graded base layer and 65-nm InP collector grown by MBE with breakdown voltage /spl sim/4 V which demonstrates the vertical scaling versus breakdown advantage over type-I DHBTs.     

Experimental determination of carrier-induced differential loss in 2-section GaInAsP/InP laser-waveguide

Measurements of threshold current density and external efficiency on broad-area laser-waveguide structure have led to the determination of the optical loss and differential loss d alpha /dN approximately=1.1-2.3 *10/sup -17/ cm/sup 2/ at lambda =1.53 mu m in a lambda /sub g/=1.30 mu m GaInAsP layer. This measurement will be useful for the design of tunable lasers.<>     

Low-frequency noise characteristics of p-n-p InAlAs/InGaAs HBTs

The low-frequency noise characteristics of p-n-p InAlAs/InGaAs heterojunction bipolar transistors (HBTs) were investigated. Devices with various geometries were measured under different bias conditions. The base noise current spectral density (3.11 /spl times/ 10/sup -16/ A/sup 2//Hz) was found to be higher than the collector noise current spectral density (1.48 /spl times/ 10/sup -16/ A/sup 2//Hz) at 10 Hz under low bias condition (I/sub C/=1 mA, V/sub EC/=1 V), while the base noise current spectral density (2.04 /spl times/ 10/sup -15/ A/sup 2//Hz) is lower than the collector noise current spectral density (7.87 /spl times/ 10/sup -15/ A/sup 2//Hz) under high bias condition (I/sub C/=10 mA, V/sub EC/=2 V). The low-frequency noise sources were identified using the emitter-feedback technique. The results suggest that the low-frequency noise is a surface-related process. In addition, the dominant noise sources varied with bias levels.     

A 130-nm 0.9-V 66-MHz 8-Mb (256K /spl times/ 32) local SONOS embedded flash EEPROM

In a 0.13-/spl mu/m CMOS logic compatible process, a 256K /spl times/ 32 bit (8 Mb) local SONOS embedded flash EEPROM was implemented using the ATD-assisted current sense amplifier (AACSA) for 0.9 V (0.7 /spl sim/ 1.4 V) low V/sub CC/ application. Read operation is performed at a high frequency of 66 MHz and shows a low current of typically 5 mA at 66-MHz operating frequency. Program operation is performed for common source array with wide I/Os (/spl times/32) by using the data-dependent source bias control scheme (DDSBCS). This novel local SONOS embedded flash EEPROM core has the cell size of 0.276 /spl mu/m/sup 2/ (16.3 F/sup 2//bit) and the program and erase time of 20 /spl mu/s and 20 ms, respectively.     

A high-speed 128-kb MRAM core for future universal memory applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.     

10-GHz power performance of a type II InP/GaAsSb DHBT

Type-II InP/GaAsSb double heterojunction bipolar transistors (DHBTs) were fabricated and microwave power performance was measured. For an InP collector thickness of 150 nm, the DHBTs show a current gain of 24, low offset voltages, and a BV/sub CEO/>6V. The 1.2/spl times/16 /spl mu/m/sup 2/ devices show f/sub T/=205GHz and f/sub MAX/=106GHz at J/sub C/=304 kA/cm/sup 2/. These devices delivered 12.6 dBm to the load at P/sub AVS/=3.3 dBm operating at 10 GHz, yielding a power-added efficiency of 41% and G/sub T/=9.3 dB.