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As technology scales down into deep-submicron, leakage energy is becoming a dominant source of energy consumption. Leakage energy is generally proportional to the area of a circuit and caches constitute a large portion of the die area. Therefore, there has been much effort to reduce leakage energy in caches. Most techniques have been targeted at cell leakage energy optimization. Bitline leakage energy is critical as well. To this end, we propose a predictive precharging scheme to reduce bitline leakage energy consumption. Results show that energy savings are significant with little performance degradation. Also, our predictive precharging is more beneficial in more aggressively scaled technologies. 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(7):877-881
In this paper, we make the case for building high-performance asymmetric-cell caches (ACCs) that employ recently-proposed asymmetric SRAMs to reduce leakage proportionally to the number of resident zero bits. Because ACCs target memory value content (independent of cell activity and access patterns), they complement prior proposals for reducing cache leakage that target memory access characteristics. Through detailed simulation and leakage estimation using a commercial 0.13-$mu$ m CMOS process model, we show that: 1) on average 75% of resident data cache bits and 64% of resident instruction cache bits are zero; 2) while prior research carefully evaluated the fraction of accessed zero bytes, we show that a high fraction of accessed zero bytes is neither a necessary nor a sufficient condition for a high fraction of resident zero bits; 3) the zero-bit program behavior persists even when we restrict our attention to live data, thereby complementing prior leakage-saving techniques that target inactive cells; and 4) ACCs can reduce leakage on the average by 4.3$times$ compared to a conventional data cache without any performance loss, and by 9$times$ at the cost of a 5% increase in overall cache access latency. 相似文献
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适于深亚微米器件模拟的Monte Carlo方法 总被引:2,自引:0,他引:2
讨论了用于深亚微米半导体器件模拟的Monte Carlo 方法(MCM),探讨了确定自由飞行时间的自散射方法,并简要阐述了玻耳兹曼模型(BTM)、漂移扩散模型(DDM)和流体动力学模型(HDM)之间的关系。 相似文献
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Singh H. Agarwal K. Sylvester D. Nowka K.J. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(11):1215-1224
The exponential increase in leakage power due to technology scaling has made power gating an attractive design choice for low-power applications. In this paper, we explore this design style in large combinational circuit blocks and latch-to-latch datapaths and introduce a novel power gating approach to yield an improved power-performance tradeoff. We first present a multiple sleep mode power gating technique where each mode represents a different point in the wake-up overhead versus leakage savings design space. We show that the high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. The multiple-mode feature allows a processor to enter power saving modes more frequently, hence, resulting in enhanced leakage savings. We apply the multimode power gating technique to datapaths where the degree of applied power gating becomes progressively stronger (harder) along the datapath. This configuration allows us to further balance wake-up overhead with leakage savings by exploiting the fact that logic circuits deep in the datapath have higher wakeup margin and hence can be strongly gated. Simulations show that multiple sleep mode capability provides an extra 17% reduction in overall leakage compared to traditional single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit. 相似文献
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本文对现代微处理器Cache设计的关键要素,包括Cache的相联度、寻址方式、透明性实现、失配处理方式、结构与层次等,进行了详细的讨论;对每一要索的各种可能选择进行了分析与比较,并讨论了这些要素在各类最新微处理器Cache设计中的实现。 相似文献
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In this paper the impact of gate leakage on 7T static random access memory (SRAM) is described and three techniques for reducing gate leakage currents and sub threshold leakage currents are examined. In first technique, the supply voltage is decreased. In the second techniques the voltage of the ground node is increased. While in third technique the effective voltage across SRAM cell Vd = 0.348V and Vs = 0.234V are observed. In all the techniques the effective voltage across SRAM cell is decreased in stand-by mode using a dynamic self controllable voltage level (SVL) switch. Simulation results based on cadence tool for 45 nm technology show that the techniques in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node voltage is increased. Result obtained show that 437 FA reductions in the leakage currents of 7T SRAM can be achieved. 相似文献
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本文提出面向访问需求的数据缓存泄漏功耗管理方法,根据访存指令对数据缓存的访问需求控制数据缓存的活动.当流水线中未发现访存指令时,将整个数据缓存保持在非活跃状态;而当发现访存指令进入流水线时,采用两种数据缓存访问控制策略以及对这两种策略的动态选择机制,在流水线早期捕获访存地址的访问需求,对数据缓存的活动作出精细控制.实验结果表明,在平均情况下,本文方法将数据缓存的泄漏功耗降低85.4%,而处理器性能提升4.41%,比传统方法在功耗与性能方面均达到更优结果. 相似文献
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Yuriko Ishitobi Tohru Ishihara Hiroto Yasuura 《Journal of Signal Processing Systems》2010,60(2):211-224
This paper proposes a code placement problem, its ILP formulation, and a heuristic algorithm for reducing the total energy
consumption of embedded processor systems including a CPU core, on-chip and off-chip memories. Our approach exploits a non-cacheable
memory region for an effective use of a cache memory and as a result, reduces the number of off-chip accesses. Our algorithm
simultaneously finds a code layout for a cacheable region, a scratchpad region, and the other non-cacheable region of the
address space so as to minimize the total energy consumption of the processor system. Experiments using a commercial embedded
processor and an off-chip SDRAM demonstrate that our algorithm reduces the energy consumption of the processor system by 23%
without any performance degradation compared to the best result achieved by the conventional approach. 相似文献
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随着集成电路制造工艺进入超深亚微米阶段,漏电流功耗在微处理器总功耗中所占的比例越来越大,在开发新的低漏流工艺和电路技术之外,如何在体系结构级控制和优化漏流功耗成为业界研究的热点.Cache在微处理器中面积最大,是进行漏流控制的首要部件.LRU是组相联Cache最常用的替换算法,而研究发现,访存操作命中LRU后半区的概率很低.LRU-Assist算法以Drowsy Cache、Cache Decay等控制策略为基础,在保证处理器性能不受影响的前提下,利用既有的LRU信息把Cache的关闭率平均提高了15%,大大降低了漏电流功耗. 相似文献
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Wireless Personal Communications - Technology scaling facilitates to meet ever increasing demands for a portable and battery operated systems, at the same time causes diminution of length of the... 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2010,18(2):184-193
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首先给出一种泄漏电流和延时的简化模型,并且在此基础上提出了一种降低泄漏电流的细粒度休眠晶体管插入法.该方法的核心是利用混合整数线性规划方法同时确定插入细粒度休眠晶体管的位置和尺寸.从实验结果可以发现,由于这种方法更好地利用了电路中的延时余量,所以在电路性能不受影响的情况下可以减小79.75%的泄漏电流;并且在一定范围内放宽电路的延时约束可以更大幅度地降低泄漏电流.与传统的固定放宽延时约束的方法相比较,当延时约束放宽7%时,这种方法可以节约74.79%的面积. 相似文献
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