Ka波段Gunn锁相源的研究

本文对Ka波段锁相源作了分析和研究,探讨了毫米波锁相环路的稳定性和相位超前补偿问题。采用双锁相环路研制了腔稳偏压调压控振荡器(VCO)、高次倍频器、低相噪微波锁相源等关键部件,采用了表面安装技术(SMT)和高密度组装技术,使研制的毫米波锁相源具有小型化、低相位噪声、高稳定度等特点。     

低相位噪声微波频率源的研究

通过对微波频率源相位噪声的分析,针对一个C波段微波频率源低相位噪声的要求,对比分析了直接倍频、数字锁相以及高频鉴相之后再倍频三种方案之间的相位噪声差别。最终得出采用直接在超高频(UHF)波段对输入信号进行模拟鉴相并锁定之后再倍频才能达到所要求的相位噪声指标。对制成的样品进行了测试,取得了预期的相位噪声指标。该C波段微波频率源的相位噪声可以达到:≤-120 dBc/Hz@1 kHz,≤-125 dBc/Hz@10 kHz,≤-130dBc/Hz@100kHz,≤-140 dBc/Hz@1 MHz。直接在UHF波段进行高频鉴相的技术,通过提高鉴相频率大幅降低了微波锁相频率源的相位噪声。     

Ka波段Gunn锁相源的研究

本文对Ｋａ波段锁相源作了分析和研究，探讨了毫米波锁相环路的稳定性和相位超前补偿问题。采用双锁相环路研制了腔稳偏压调压控振荡器，高次倍频器，低相噪微波锁相源等关键部件，采用了表面安装技术和高密度组装技术，使研制的毫米滤锁相源具有小型化、低相位噪声高稳定度等特点。     

3mm锁相源研究及系统应用

采用双环数字锁相方式完成3mm波锁相源研究,并成功应用于国内第一套“95GHz毫米波干涉仪”测速系统。提出了一种新的毫米波双环锁相源相位噪声估测方法。实验结果表明:该毫米波锁相源工作在95GHz时,输出功率大于10mW,相位噪声达到-59dBc/Hz@10kHz,在-10℃~ 45℃温度范围内的频率稳定度为1.2×10-6,完全满足测速系统对毫米波发射源的高稳定、高精确度技术要求。     

8mm小型化低相位噪声锁相源

依据小型化、低相位噪声原则设计了毫米波锁相源．在实现方案中，选用了高性能的锁相环、分频器和集成ＶＣＯ等器件；结构上采用了毫米波高密度组装技术和ＳＭＴ技术，使研制成功的毫米波锁相源具有体积小、相位噪声低、入锁快和可靠性好等特点，可适用于机载、弹载等许多场合．     

低相噪毫米波源的研制

介绍了一种毫米波低相噪源的设计方法,采用PDRO和倍频电路方案,对本微波源的相位噪声和频率稳定度进行了分析,并简要介绍了PDRO的设计,对研制成的实物进行了测试,达到了设计要求的指标。该毫米波源的相位噪声≤-95dBc/Hz@10kHz,频率稳定度Δfout/fout≤1×10-8,杂波抑制比rs≤-75dBc。该毫米波源具有相位噪声低、体积小、Q值高、频率温度稳定性好等优点,具有广阔的应用前景。     

低相噪捷变频毫米波频率源的研制

基于整数和小数分频锁相原理,采用双锁相源+混频方案,实现了一种可用于毫米波雷达系统的低相噪、小步进、捷变频毫米波频率源。实测结果表明:该频率源产品在31.0~32.5GHz频带范围内,相位噪声可达-90dBc/Hz@1kHz,跳频时间小于10μs,跳频步进100kHz,最低杂散抑制低于-60dBc。     

一款低相位噪声分谐波采样锁相振荡源的设计

现介绍了一种低相位噪声锁相振荡源，以分谐波采样式鉴相取代传统的分频式鉴相。这种方案除了压控振荡器是高频微波部件外，其余都可以用集总参数的电路构成，系统的结构较简单，便于实现小型化，突出优点在于它的灵活性，一个宽带取样鉴相器可对各个频段的压拉振荡器直接进行取样鉴相和锁相。在同等条件下，分谐波采样式锁相源比分频式锁相源的相位噪声更低。     

一种改善频率合成器相位噪声的方法

在现代电子技术中,数字式频率合成器在通信、雷达等系统中得到了广泛的应用,其相位噪声直接影响到系统的整体性能。提出了利用变频锁相方法改善微波波段频率合成器的相位噪声,并进行了频域分析,给出了相应的环路滤波器的设计。最后的实验结果给出了变频锁相与直接锁相的频率合成器相位噪声比较,可以看出采用变频锁相方式的频率合成器的相位噪声有了很大的改善。     

模拟锁相陶瓷介质振荡器技术

通过对模拟锁相频率源及传统方法实现的锁相频率源进行简要的分析比较,在分析取样鉴相器工作原理的基础上给出了模拟锁相CRO的具体实现方案。重点介绍了环路滤波电路及自动捕获电路的工作原理及参数设置,同时也给出了改进输出信号杂波抑制的方法。设计所得到的模拟锁相CRO,其相位噪声指标是采用一般的锁相方式难以获得的。实测表明模拟锁相CRO的相位噪声较低,输出频率3 GHz,相位噪声可以达到≤–115 dBc/Hz@10 kHz,杂波抑制指标也有一定的优势,可以达到优于–70 dBc。     

Phase Noise Analysis and Estimate of Millimeter Wave PLL Frequency Synthesizer

Phase noise is an important index in evaluating the performance of millimeter wave (MMW) frequency source. Because of the high frequency, it is difficult to measure its phase noise directly. So it is very necessary to find new methods for estimating it effectively and easily. In this paper, the main factors affecting phase noise of MMW PLL frequency source are analyzed, and then a new method to estimate the phase noise is presented, which is based on the comparison of the phase noise of microwave phase-locked frequency source with phase-locked intermediate frequency in MMW phase-locked loop. In order to demonstrate the validity of this method of phase noise estimate, it is applied to estimate the phase noise of 95GHz double PLL frequency synthesizer. The result shows that the theoretical estimate value is well coincident with the experimental value.     

A Millimeter Wave Phase Locked and Frequency Multiplying Source

A millimeter wave phase locked and frequency multiplying source is proposed in this paper. The design includes an X-band phase locked loop (PLL) frequency synthesizer as the base frequency source, and a monolithic millimeter wave frequency tripler, which is developed by using OMMIC 0.18μm pHEMT process. The PLL and the tripler are integrated in a single circuit board to make a low-cost and compact frequency source with the size of 6cm × 5cm. Measurement shows an output power of more than 4.8dBm at the frequency range from 35 to 36.7GHz. A phase noise of about -92dBc/Hz at 100kHz offset is achieved.     

A millimeter wave frequency synthesizer covering the 40–60 GHz waveguide band

This paper describes a millimeter wave frequency synthesizer based on a single broadband backward wave oscillator tube which is capable of covering the entire 40–60 GHz waveguide band with useful power output, low phase noise, and rapid frequency switching. The synthesizer is controlled by an internal microcomputer which sets the reference oscillator frequency through a General Purpose Interface Bus (GPIB) and generates synthesizer coarse tuning corrections through a programmable digital-to-analog converter. The phase/frequency control system uses a frequency discriminator for capture of the source from large frequency errors and a complementary phase lock for precise phase and frequency control.     

低相位噪声微波振荡器设计

针对Ka和Ku波段上、下变频装置对微波振荡器低相位噪声和小型化的要求,该文采用单环锁相式频率合成技术完成了微波振荡器的设计,并对锁相环的相位噪声进行了理论计算。分析了鉴相频率、鉴相器灵敏度和环路带宽对锁相环输出相位噪声的影响,根据分析结果对微波振荡器电路参数合理选择,同时兼顾了低相位噪声与小型化的设计要求。测试结果表明,振荡器的相位噪声指标与理论计算一致,各项指标均达到要求,可满足实际工程应用。     

An Approach of Developing High Performance Millimeter-wave Frequency Synthesizer

In this paper, an approach of developing high performance millimeter-wave frequency synthesizer is proposed, which is significantly simpler than the conventional cases. The synthesizer is driven by one triple tuned typed synthesizer, which adjusts the output frequency of DDS and frequency division ratios of variable frequency divider to suppress the spurious level. With the proposed method, a microwave phase locked loop (PLL) PE3236 and a millimeter-wave multiplier HMC283 are also used. Moreover, the PLL is implemented with the form of charge pump followed by a passive three-order low-pass filter which can further suppress the phase noise. Finally, a low spurious level and high frequency resolution millimeter-wave frequency synthesizer without degradation of frequency switching speed is developed. Experimental results show that this method can achieve the performances of low spurious level, low phase noise, and high frequency resolution.     

一种宽带低相噪频率合成器的设计方法研究

提出了一种宽带低相噪频率合成器的设计方法.采用了数字锁相技术,该锁相技术主要由锁相环（phase locked loop,PLL）芯片、有源环路滤波器、宽带压控振荡器和外置宽带分频器等构成,实现了10~20 GHz范围内任意频率输出,具有输出频率宽、相位噪声低、集成度高、功耗低和成本低等优点.最后对该PLL电路杂散抑制和相位噪声的指标进行了测试,测试结果表明该PLL输出10 GHz时相位噪声优于-109 dBc/Hz@1 kHz,该指标与直接式频率合成器实现的指标相当.     

Ramsey-CPT原子频标的高性能小型脉冲微波源研究

根据Ramsey-CPT原子频标对脉冲微波源高性能小型化的要求,采用直接数字频率合成器（DDS）激励锁相环频率合成器,再结合可编程数字功率衰减器和阻抗匹配电路,从而实现具有高稳定度、高分辨率、快跳频速度、低相位噪声、小体积、小步长扫描的脉冲微波源。比较应用于Ramsey-CPT原子频标的脉冲微波源方案,介绍脉冲微波源的基本原理,简述其具体实现方法,并通过仿真优化得到最佳的输出性能。实现的脉冲微波源具有优良的技术性能,进一步提高了Ramsey-CPT原子频标输出频率的性能。同时,达到了设计小型化的要求,有利于Ramsey-CPT原子频标的便携式应用。     

微波取样锁相频率合成器的设计

阐述了微波接收机中的相位噪声概念及本振源频率不稳定度的实际测量参数,并简要介绍了频率合成技术和锁相环路工作原理.针对卫星电视接收机中微波高稳定本振源的要求,重点研究了取样锁相频率合成器电路的优化设计及性能.     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.