Materials and processes for implementing high-temperature liquid interconnects

This paper describes the results of a study investigating liquid solder joints at elevated temperatures (up to 200/spl deg/C). The reactions of eutectic 52In/48Sn solder, which melts at 118/spl deg/C, with various metal barrier layers is presented. The main emphasis of the research was to find a combination of solder and substrate metallization which has good adhesion strength but also remains stable during temperature cycling and high-temperature storage when the solder is molten. Intermetallic growth rates and solder-substrate adhesion strength have been measured for a range of potential barrier layers including Ni, Cr, Pt, Ti, V, Nb, Ta, and W. Of these, only Nb was found to have acceptable properties for a high-temperature barrier layer to In/Sn solder. Other aspects of liquid solder interconnections that have been studied include stability of the molten solder-underfill interface under electrical bias and retention of electrical contact during vibration and phase change. Plastic ball grid array (PBGA) devices have been assembled with Nb barrier layers and liquid solder joints and their reliability during temperature cycling (-20/spl deg/C to +180/spl deg/C) has been compared to PBGA joints with Sn95.5/Ag4/Cu0.5 solder balls.     

Achievement of homogeneous AuSn solder by pulsed laser-assisted deposition

The deposition of AuSn solder at the eutectic composition (80 wt.% Au, 20 wt.% Sn) on a wetted, chemically inert metallic barrier has been studied in relation to its use in optoelectronic packaging. The bonding structure, consisting of a W barrier, the top part of which is doped with Ni (or Ti) to provide wetting by molten AuSn, and the homogeneous 80–20 AuSn solder several micrometers thick, has been grown by the Pulsed Laser-assisted Deposition (PLD) technique on 2″ silicon wafers. The composition of the AuSn layer was controlled within better than 1 wt.% as probed by EDX across the wafer diameter. The molten solder exhibited good wetting properties on the W modified layer and the whole structure was found to be chemically stable against thermal cycling at 320°C for over 3 min. The use of molten AuSn targets makes the PLD technique a most competitive one for the achievement of high quality and reliable AuSn solder.     

Investigation of flip chip under bump metallization systems of Cupads

In this study, UBM material systems for flip chip solder bumps on Cu pads were investigated using the electroless copper (E-Cu) and electroless nickel (E-Ni) plating methods; and the effects of the interfacial reaction between UBMs and Sn-36Pb-2Ag solders on the solder bump joint reliability were also investigated to optimize UBM materials for flip chip on Cu pads. For the E-Cu UBM, scallop-like Cu₆Sn₅, intermetallic compound (IMC) forms at the solder/E-Cu interface, and bump fracture occurred along this interface under a relatively small load. In contrast, at the E-Ni/E-Cu UBM, E-Ni serves as a good diffusion-barrier layer. The E-Ni effectively limited the growth of the IMC at the interface, and the polygonal-shape Ni₃ Sn₄ IMC resulted in a relatively higher adhesion strength compared with the E-Cu UBM. As a result, electroless deposited UBM systems were successfully demonstrated as low cost UBM alternatives on Cu pads. It was found that the E-Ni/E-Cu UBM material system was a better choice for solder flip chip interconnection on Cu pads than the E-Cu UBM     

Failure Morphology After Drop Impact Test of Ball Grid Array (BGA) Package With Lead-Free Sn–3.8Ag–0.7Cu and Eutectic SnPb Solders

High strain-rate drop impact tests were performed on ball grid array (BGA) packages with solder compositions of (in wt%) Sn-3.8Ag-0.7Cu (SnAgCu) and eutectic Sn-37Pb (SnPb). Solder balls were joined to the metallizations of plated Ni on the device side and plated Cu on the board side. The BGA packages were tested at 1500 g within 0.5 ms, resulting in an imposed bending strain of 0.2-0.3%. Both SnAgCu and SnPb joints failed at the interface at the device side but the detailed failure morphology differed significantly. The crack location for the eutectic SnPb was primarily through the solder and seldom extended through an entire bump. The SnPb joints also exhibited bulk solder deformation. The SnAgCu joints showed extremely brittle behavior with an interfacial failure at the (Ni,Cu)₃Sn₄ intermetallics/Ni under bump metallization (UBM) interface. The strain rate sensitivity of bulk solder defines the drop test performance and the eutectic SnPb solder showed better drop impact performance due to a less strain rate sensitivity     

Wetting reaction of Sn-Ag based solder systems on Cu substrates plated with Au and/or Pd layer

The wetting behavior of SnAg based Pb-free solders on Cu and Cu substrates plated with Au, Pd, and Au/Pd thin films have been studied. The wetting angle and kinetics of interfacial reaction were measured. The Au-plated substrates exhibit better wetting than the Pd-plated substrates. In the case of SnAg on Pd-plated Cu, SEM observation revealed that the solder cap was surrounded by an innerring of Cu−Sn compound and an outer ring of Pd−Sn compound. This implies that the molten SnAg solder had removed the Pd and wetted the Cu directly in the equilibrium state. The effects of pre-doping Cu in the SnAg solder on wetting behavior were also investigated. We found that wettability decreases with increasing Cu content in the solder. We also observed that the SnAgCu solders have a lower Cu consumption rate than the SnAg solder.     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

Effects of substrate metallization of solder/under-bump metallization interfacial reactions in flip-chip packages during multiple reflow cycles

The effects of various elements of substrate metallization, namely, Au, Ni, and P, on the solder/under-bump metallization (UBM), (Al/Ni(V)/Cu) interfacial reactions in flip-chip packages during multiple reflow processes were systematically investigated. It was found that Au and P had negligible effects on the liquid-solid interfacial reactions. However, Ni in the substrate metallization greatly accelerated the interfacial reactions at chip side and degraded the thermal stability of the UBM through formation of a (Cu,Ni)₆Sn₅ ternary compound at the solder/UBM interface. This phenomenon can be explained in terms of enhanced grain-boundary grooving on (Cu,Ni)₆Sn₅ in the molten solder during the reflow process. This could eventually cause the rapid spalling of an intermetallic compound (IMC) from the solder/UBM interface and early failure of the packages. Our results showed that formation of multicomponent intermetallics, such as (Cu,Ni)₆Sn₅ or (Ni,Cu)₃Sn₄, at the solder/UBM interface is detrimental to the solder-joint reliability.     

Fundamental Study of the Intermixing of 95Pb-5Sn High-Lead Solder Bumps and 37Pb-63Sn Pre-Solder on Chip-Carrier Substrates

This study investigated the intermixing of 95Pb-5Sn solder bumps and 37Pb-63Sn pre-solder in flip-chip solder joints. The reaction conditions included multiple reflows (up to ten) at 240°C, whereby previously solder-coated parts are joined by heating without using additional solder. We found that the molten pre-solder had an irregular shape similar to a calyx (i.e., a cup-like structure) wrapped around a high-lead solder bump. The height to which the molten pre-solder ascended along the solid high-lead solder bump increased with the number of reflows. The molten pre-solder was able to reach the under bump metallurgy (UBM)/95Pb-5Sn interface after three to five reflows. The molten pre-solder at the UBM/95Pb-5Sn interface generated two important phenomena: (1) the molten solder dewetted (i.e., flowed away from the soldered surface) along the UBM/95Pb-5Sn interface, particularly when the number of reflows was high, and (2) the molten pre-solder transported Cu␣atoms to the UBM/95Pb-5Sn interface, which in turn caused the Ni-Sn compounds at the chip-side interface to change into (Cu_0.6Ni_0.4)₆Sn₅.     

预成型焊片润湿性动态测试方法

预成型焊片的润湿性直接关系到光电子封装的可靠性。常用的焊料润湿性评价方法对于评价预成型焊片润湿性具有很大局限性。提出了一种动态测试焊料润湿性的方法,并设计了一套测试系统。通过铺展面积与时间的关系曲线得出最大铺展面积、润湿时间、平均润湿速度和瞬时润湿速度等特征参数,对预成型焊片的润湿性进行评价。实验表明,该润湿性动态测试...     

Lead-Free Solders in IC Manufacture: A Review

The compositions and melting points of lead-free solders suitable for IC packaging are given. The use of tin–bismuth alloys for both this purpose and the corrosion protection of packages is outlined. An investigation is described into the dissolution of 0.04-mm-thick gold wire in the POIn50 tin–indium solder in the molten or solid state. In the former case the process is examined as a function of solder temperature and the contact time between the molten solder and the wire. In the latter case, dissolution kinetics is studied at 100°C. The soldering of gold-coated hybrid-IC substrates, including microwave ones, to metal bases is addressed. In this context an analysis of the interaction between the POIn50 solder and the gold coating is presented.     

Solder joint reliability of indium-alloy interconnection

Recent high-density very large scale integrated (VLSI) interconnections in multichip modules require high-reliability solder interconnection to enable us to achieve small interconnect size andlarge number of input/output terminals, and to minimize soft errors in VLSIs induced by α-particle emission from solder. Lead-free solders such as indium (In)-alloy solders are a possible alternative to conventional lead-tin (Pb-Sn) solders. To realize reliable interconnections using In-alloy solders, fatigue behavior, finite element method (FEM) simulations, and dissolution and reaction between solder and metallization were studied with flip-chip interconnection models. We measured the fatigue life of solder joints and the mechanical properties of solders, and compared the results with a computer simulation based on the FEM. Indium-alloy solders have better mechanical properties for solder joints, and their flip-chip interconnection models showed a longer fatigue life than that of Pb-Sn solder in thermal shock tests between liquid nitrogen and room temperatures. The fatigue characteristics obtained by experiment agree with that given by FEM analysis. Dissolution tests show that Pt film is resistant to dissolution into In solder, indicating that Pt is an adequate barrier layer material for In solder. This test also shows that Au dissolution into the In-Sn solder raises its melting point; however, Ag addition to In-Sn solder prevents melting point rise. Experimental results show that In-alloy solders are suitable for fabricating reliable interconnections.     

The Influence of Substrate Enhancement on Moisture Sensitivity Level (MSL) Performance for Green PBGA Packages

As the electronics industry migrates to the lead- and halogen-free (green) packages, many of the materials used in plastic ball-grid array (PBGA) substrates, in particular the molding compounds and die attaches, will have to be improved. The moisture sensitivity level (MSL) performance of the large nongreen PBGA packages are typically reduced by at least one JEDEC/IPC level at the lead-free reflow temperature of 260$^circ$C. Common failure mechanisms of traditional large size PBGA packages include popcorning, as well as delamination and cracks between the solder mask/copper interface in the multiple layer substrates. In this paper, the interfacial adhesion of traditional and advanced substrate materials and processing technologies are presented based on reliability tests of various PBGA packages subject to moisture soaking followed by reflow soldering at 260$^circ$C. It was found that substrate failures with delamination at the solder mask/copper interface were dramatically improved by introducing advanced materials and processes for multiple-layer substrates. However, the partial or full delamination at the mold compound/solder mask interface could still be observed after lead-free reflow soldering. There is an urgent need to improve the adhesion between mold compound/solder mask in order to achieve high MSL performance of large size and green PBGA packages.     

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.     

Effect of Size of Lid-Substrate Adhesive on Reliability of Solder Balls in Thermally Enhanced Flip Chip PBGA Packages

Six design cases of lid-substrate adhesive with various combinations of widths and heights were analyzed to investigate how the size of the adhesive affects the reliability of the solder balls of thermally enhanced flip chip plastic ball grid array (FC-PBGA) packages in thermal cycling tests. Analysis results were compared with data on the reliability of conventional FC-PBGA packages. Thermal-mechanical behavior was simulated by the finite element (FE) method and the eutectic solder was assumed to exhibit elastic-viscoplastic behavior. The temperature-dependent nonlinear stress/strain relationship of the adhesive was experimentally determined and used in the FE analysis. Darveaux's model was employed to obtain the predicted fatigue life of the solder ball. Simulation results reveal that the fatigue life of the solder balls in thermally enhanced FC-PBGA packages is much shorter than that in conventional FC-PBGA packages, and the life of solder balls increases with both the width and the height of the adhesive. However, the effect of the width of the adhesive on the reliability of the solder ball is stronger than that of the height. Moreover, increasing either the width or the height reduces the plastic strain in the adhesive at critical locations, indicating that the reliability of the adhesive can be improved by its size. The predicted results of the life of solder balls for some selected studied packages are also compared with experimental data from thermal cycling tests in the paper     

Study of wetting reaction between eutectic AuSn and Au foil

Wetting reactions between eutectic AuSn solder and Au foil have been studied. During the reflow process, Au foil dissolution occurred at the interface of AuSn/Au, which increases with temperature and time. The activation energy for Au dissolution in molten AuSn solder is determined to be 41.7 kJ/mol. Au₅Sn is the dominant interfacial compound phase formed at the interface. The activation energy for the growth of the interfacial Au₅Sn phase layer is 54.3 kJ/mol over the temperature range 360–440°C. The best wettability of molten AuSn solder balls on Au foils occurred at 390°C (wetting angle is about 25°). Above 390°C, the higher solder oxidation rate retarded the wetting of the molten AuSn solder.     

Reaction kinetics of solder-balls with pads in BGA packages during reflow soldering

The Au/Ni/Cu three-layer structure is one of the most common solder-ball pad finishes for the ball-grid-array (BGA) packages. The first layer, which is to be in direct contact with the solder, is a 1-μm Au layer. Beneath the Au layer is the Ni layer, whose thickness is about 7 μm. The Cu layer is part of the internal wiring of a BGA package. In this study, eutectic PbSn solder-balls were reflowed on the Au/Ni/Cu pads at 225°C for reflow times from 7.5 s to 1003 s. It was found that the Au layer reacted very quickly with the solder to form AuSn₄ and AuSn₂. The growth rate of AuSn₄ + AuSn₂ was very high, approaching 1 μm/s. When the reflow time reached 10 s, all the Au had been consumed, and AuSn₂ had been converted to AuSn₄. Moreover, AuSn₄ grains began to separate themselves from the Ni layer at the roots of the grains, and started to fall into the solder. When the reflow time reached 30 s, all AuSn₄ grains had left the interface and a thin layer of Ni₃Sn₄ formed at the solder-Ni interface. The growth rate of this Ni₃Sn₄ layer was very low, reaching only 6 μm for 1003 s of reflow. This study showed that during reflow the Au layer reacted with Sn to form AuSn₄ first, and then broke off and fell into the molten solder. In other words, the Au layer did not dissolve into the molten solder directly during reflow.     

Ceramic packages for liquid-nitrogen operation

To evaluate their compatibility for use in a liquid-nitrogen computer, metallized ceramic packages with test chips using controlled-collapse solder (Pb-Sn) technology were cycled between 30°C and liquid-nitrogen temperature. Room-temperature electrical resistance measurements were made at regular intervals of cycles to determine whether solder failure accompanied by a significant resistance increase had occurred. For the failed solder joints characterized by the highest thermal shear strain amplitude of 3.3%, it was possible to estimate the number of liquid-nitrogen cycles needed to produce the corresponding failure rate using a room-temperature solder lifetime model. Cross-sectional examination of the failed solder joints using scanning electron microscopy (SEM) and energy-dispersive X-ray analysis indicated solder cracking occurring at the solder-ceramic interface. Chip-pull tests on cycled packages yielded strengths far exceeding the minimal requirement. Mechanisms involving the formation of intermetallics are proposed to account for the observed solder fracture modes after liquid-nitrogen cycling and after chip pull. SEM examination of pulled chips in cycled packages found no apparent sign of cracking in quartz and polyimide for chip insulation     

Interfacial reaction and solder joint reliability of Pb-free solders in lead frame chip scale packages (LF-CSP)

Chip scale packages (CSP) have essential solder joint quality problems, and a board level reliability is a key issue in design and development of the CSP type packages. There has been an effort to eliminate Pb from solder due to its toxicology. To evaluate the various solder balls in CSP package applications, Pb-free Sn-Ag-X (X=In, Cu, Bi) and Sn-9Zn-1Bi-5In solder balls were characterized by melting behavior, phases, interfacial reaction, and solder joint reliability. For studying joint strength between solders and under bump metallurgy (UBM) systems, various UBMs were prepared by electroplating and electroless plating. After T/C (temperature cycle) test, Sn3.5Ag8.5In solder was partially corroded and its shape was distorted. This phenomenon was observed in a Sn3Ag10In 1Cu solder system, too. Their fractured surface, microstructure of solder joint interface, and of bulk solder ball were examined and analyzed by optical microscopy, SEM and EDX. To simulate the real surface mounting condition and evaluate the solder joint reliability on board level, Daisy chain test samples using LF-CSP packages were prepared with various Pb-free solders, then a temperature cycle test (−65∼ 150°C) was performed. All tested Pb-free solders showed better board level solder joint reliability than Sn-36Pb-2Ag. Sn-3.5Ag-0.7Cu and Sn-9Zn-1Bi-5In solders showed 35%, 100% superior solder joint reliability than Sn-36Pb-2Ag solder ball, respectively.     

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7/spl deg/C. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps.     

Experimental Wetting Dynamics Study of Eutectic and Lead-Free Solders With Various Fluxes, Isothermal Conditions, and Bond Pad Metallizations

Demands on solder bump interconnects have increased in modern electronics. This is characterized by high density, small size, and fine-pitch devices. In solder bump interconnects, solder wetting onto bond pads is the key factor that determines the interconnect process yield and the solder joint reliability. Solder wetting involves various physical phenomena such as surface tension imbalance, viscous dissipation, molecular kinetic motion, chemical reaction, and diffusion. In this paper, an experimental study on solder wetting dynamics will be presented. The effects of solder reflow process parameters and bonding materials will be discussed, as they relate to the physics of solder wetting and ultimately the interconnect process yield and solder joint reliability. The experimental setup consists of a high-speed image acquisition system and a temperature chamber which were used to measure the time dependent behavior of molten solder spheres onto bond pads under an isothermal condition. The solder materials investigated were eutectic tin–lead solder and lead-free 95.5Sn–4.0Ag–0.5Cu solder. The wetting dynamics of the solder materials were investigated on pure Cu bond pads and Cu/Ni/Au bond pads, with several different flux systems, at different environmental temperatures and with various solder sphere sizes. The experimental observations indicate that the wetting dynamics clearly depend on temperature, solder materials, and substrate metallization but do not depend significantly on the flux system or the solder sphere size.