一种基于ZigBee应用的低功耗2.4GHz无线收发机

This paper presents a low power 2.4 GHz transceiver for ZigBee applications.This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter.The receiver consists of a new low noise amplifier(LNA) with a noise cancellation function,a new inverter-based variable gain complex filter (VGCF) for image rejection,a passive quadrature mixer,and a decibel linear programmable gain amplifier(PGA). The transmitter adopts a quadrature mixer and a class-B mode variable gain power amplifier(PA) to reduce power consumption.This transceiver is implemented in 0.18μm CMOS technology.The receiver achieves—95 dBm of sensitivity,28 dBc of image rejection,and -8 dBm of third-order input intercept point(IIP3).The transmitter can deliver a maximum of+3 dBm output power with PA efficiency of 30%.The whole chip area is less than 4.32 mm~2. It only consumes 12.63 mW in receiving mode and 14.22 mW in transmitting mode,respectively.     

一种用于短距离无线通信的低功耗多频带可配置收发机

A reconfigurable multi-mode multi-band transceiver for low power short-range wireless communication applications is presented.Its low intermediate frequency(IF) receiver with 3 MHz IF carrier frequency and the direct-conversion transmitter support reconfigurable signal bandwidths from 250 kHz to 2 MHz and support a highest data rate of 3 Mbps for MSK modulation.An integrated multi-band PLL frequency synthesizer is utilized to provide the quadrature LO signals from about 300 MHz to 1 GHz for the transceiver multi-band application. The transceiver has been implemented in a 0.18μm CMOS process.The measurement results at the maximum gain mode show that the receiver achieves a noise figure(NF) of 4.9/5.5 dB and an input 3rd order intermodulation point(IIP3) of-19.6/-18.2 dBm in 400/900 MHz band.The transmitter working in 400/900 MHz band can deliver 10.2/7.3 dBm power to a 50Ωload.The transceiver consumes 32.9/35.6 mW in receive mode and 47.4/50.1 mW in transmit mode in 400/900 MHz band,respectively.     

一款便携式移动应用的低成本超高频无源射频识别读写器收发机芯片设计

A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads.     

Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer

This paper explores an energy-efficient pulsed ultra-wideband (UWB) radio-frequency (RF) front-end chip fabricated in 0.18-μm CMOS technology,including a transmitter,receiver,and fractional synthesizer.The transmitter adopts a digital offset quadrature phase-shift keying (O-QPSK) modulator and passive direct-phase multiplexing technology,which are energy-and hardware-efficient,to enhance the data rate for a given spectrum.A passive mixer and a capacitor cross-coupled (CCC) source-follower driving amplifier (DA) are also designed for the transmitter to further reduce the low power consumption.For the receiver,a power-aware low-noise amplifier (LNA) and a quadrature mixer are applied.The LNA adopts a CCC boost common-gate amplifier as the input stage,and its current is reused for the second stage to save power.The mixer uses a shared amplification stage for the following passive IQ mixer.Phase noise suppression of the phase-locked loop (PLL) is achieved by utilizing an even-harmonics-nulled series-coupled quadrature oscillator (QVCO) and an in-band noise-aware charge pump (CP) design.The transceiver achieves a measured data rate of 0.8 Gbps with power consumption of 16 mW and 31.5 mW for the transmitter and the receiver,respectively.The optimized integrated phase noise of the PLL is 0.52° at 4.025 GHz.     

应用于2.4GHz无线传感网的超低功耗射频接收前端设计

This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network （WSN） in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate （CG） LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure （NF） at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point （IPldB） at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.     

应用于802.11b无线局域网的单芯片低功耗CMOS收发机

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta （∑△） fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of -3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7 × 4.2 mm^2.     

A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS

This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186μm^2 and consumes 5.3 mW power.     

A 5 Gb/s transceiver in 0.13μm CMOS for PCIE2.0

This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC’s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm~2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.     

基于北斗、GPS双模双通道的镜像抑制接收机射频前端设计

This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass(Beidou) and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm~2 areas,and 8 mA of current in 0.18μm TSMC CMOS process.Except for a few passive components for input matching,other components such as an off-chip low noise amplifier or a balun are not required.With a non-tunable passive image rejection filter,the receiver frontend can achieve around 60 dB gain and 34 dB image rejection.     

An ultra-low-power RF transceiver for WBANs in medical applications

A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks(WBANs)in medical applications is presented.The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs.The transceiver consists of a main receiver(RX)with an ultra-low-power free-running ring oscillator and a high speed main transmitter(TX)with fast lock-in PLL.A passive wake-up receiver(WuRx)for wake-up function with a high power conversion efficiency(PCE)CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power.The chip is implemented in a 0.18μm CMOS process.Its core area is 1.6 mm~2. The main RX achieves a sensitivity of-55 dBm at a 100 kbps OOK data rate while consuming just 210μA current from the 1 V power supply.The main TX achieves +3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than 25%.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

基于反熔丝结构的低成本嵌入式一次可编程4-kbit 存储器宏

A 4-kbit low-cost one-time programmable （OTP） memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor （1.5T） OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch （HVSW） circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification （RFID） tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600 × 600 μm2. The 4-kbit OTP macro only consumes 200 × 260 μm^2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.     

A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect

In analog circuit design an important parameter,from the perspective of superior device performance,is linearity.The DG MOSFET in asymmetric mode operation has been found to present a better linearity.In addition to that it provides,at the discretion of analog circuit designer,an additional degree of freedom,by providing independent bias control for the front and the back gates.Here a non-quasi-static(NQS)small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD simulations.The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance,Cgd1and Cgd2,the intrinsic front and back distributed channel resistance,Rgd1and Rgd2respectively,the transport delay,m,and the inductance,Lsd.The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data,for symmetric DG MOSFET devices,from the available literature.The device simulation is performed with respect to frequency up to 100 GHz.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

用于无采保流水线ADC的高速低功耗低失调动态比较器

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

一种应用于无线局域网具有3.01-3.82 GHz频率范围和6.29%调谐增益变化的CMOS LC压控振荡器

A wideband low-phase-noise LC voltage-controlled oscillator （VCO） with low VCO gain （Kvco） vari- ation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low Kvco variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured Kvco is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of-121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.