88 nm栅长fmax＝201 GHz InP基In0.53Ga0.47As/In0.52Al0.48As HEMT器件

我们成功研制了栅长88 nm, 栅宽2 50 μm, 源漏间距为2.4 μm 的InP基In0.53Ga0.47As/In0.52Al0.48As高电子迁移率器件(HEMT)。栅是使用PMMA/Al/UVⅢ,通过优化电子束曝光时间及其显影时间的方式制作的。这些器件有比较好的直流及其射频特性：峰值跨导、最大源漏饱和电流密度、开启电压、ft和fmax 分别为765 mS/mm, 591 mA/mm, -0.5 V, 150 GHz 和201 GHz。这些器件将非常适合于毫米波段集成电路。     

Optimized power simulation of AlGaN/GaN HEMT for continuous wave and pulse applications

An optimized modeling method of 8 × 100 μm AlGaN/GaN-based high electron mobility transistor (HEMT) for accurate continuous wave (CW) and pulsed power simulations is proposed. Since the self-heating effect can occur during the continuous operation, the power gain from the continuous operation significantly decreases when compared to a pulsed power operation. This paper extracts power performances of different device models from different quiescent biases of pulsed current-voltage (I-V) measurements and compared them in order to determine the most suitable device model for CW and pulse RF microwave power amplifier design. The simulated output power and gain results of the models at V_gs = -3.5 V, V_ds = 30 V with a frequency of 9.6 GHz are presented.     

Sn掺杂对(In0.95-xSnxFe0.05)2O3薄膜的结构、电学及磁特性的影响

我们利用脉冲激光沉积的方法制备了一系列(In0.95-xSnxFe0.05)2O3 (x=0~0.09)薄膜,并在其中发现了室温铁磁性。X射线衍射结果表明锡与铁离子已掺入氧化铟晶格。随着锡的掺入,样品内的载流子浓度得到了很大的提高,但相应的铁磁性却几乎没有变化。我们认为氧空位相关的束缚磁极化子模型能够跟好的解释我们的铁掺杂氧化铟薄膜中的铁磁耦合的机制,而载流子传导的RKKY相互作用则不适用于这一系统。     

微波法制备高活性H1-xSr2Nb3-xMoxO10 (x = 0, 0.05, 0.1, 0.15 and 0.2) 光催化剂

通过微波辅助法制备出高活性H1-xSr2Nb3-xMoxO10光催化材料,制备过程和时间均被大大缩短。采用X射线粉末衍射（XRD）、扫描电镜（SEM）、紫外-可见吸收吸收光谱（UV-Vis DRS）等表征其材料性能。考察了催化材料在40W汞灯辐照下催化降解甲基橙的催化性能。实验结果表明,MoO3的掺入量为15%（摩尔分数）时,材料的光催化性能最优。     

CH3NH3PbI3/p-Si异质结的光电特性研究

利用一步溶液法在p型Si衬底上生长有机/无机杂化钙钛矿CH3NH3PbI3薄膜,构成CH3NH3PbI3/p-Si异质结。利用原子力显微镜(AFM)、扫描电子显微镜(SEM)对薄膜形貌和结构进行表征,通过无光照和有光照条件下的电流-电压(I-V)、电容-电压(C-V)测试对异质结的光电特性进行研究。I-V测试结果显示CH3NH3PbI3/p-Si异质结具有整流特性,正反偏压为±5V时,整流比大于70,并在此异质结上观察到了光电转换现象,开路电压为10mV,短路电流为0.16uA。C-V测试结果显示Ag/CH3NH3PbI3/p-Si异质结具有与MIS(金属-绝缘层-半导体)结构相似的C-V特性曲线,与理想MIS的C-V特性曲线相比,异质结的C-V曲线整体沿电压轴向正电压方向平移。C-V特性曲线的这种平移表明Ag/CH3NH3PbI3/p-Si异质结界面存在界面缺陷,CH3NH3PbI3层也可能存在固定电荷。这种界面缺陷是导致CH3NH3PbI3/p-Si异质结开路电压的大幅度降低的重要原因。此外,CH3NH3PbI3薄膜的C-V测试结果显示其具有介电非线性特性,其介电常数约为4.64。     

Performance improvement of c-Si solar cell by a combination of SiNx/SiOx passivation and double P-diffusion gettering treatment

SiN_x/SiO_x passivation and double side P-diffusion gettering treatment have been used for the fabrication of c-Si solar cells. The solar cells fabricated have high open circuit voltage and short circuit current after the double P-diffusion treatment. In addition to better surface passivation effect, SiN_x/SiO_x layer has lower reflectivity in long wavelength range than conventional SiN_x film. As a consequence, such solar cells exhibit higher conversion efficiency and better internal quantum efficiency, compared with conventional c-Si solar cells.     

高峰谷电流比的高掺杂发射区In0.53Ga0.47As/AlAs共振隧穿二极管

利用空气桥工艺设计和制作了高掺杂发射区In0.53Ga0.47As/AlAs共振隧穿二极管（RTD）。在室温下,器件的峰谷电流比大于40,峰值电流密度为24kA/cm2。建立了RTD器件等效电路模型,并从直流和微波测试结果中提取出器件参数。高峰谷电流比的RTD器件具有非常小的电容,有利于在微波/太赫兹领域中的应用。     

Nanoscale analysis of YBa2Cu3O7−x/La0.67Ca0.33MnO3 interfaces

The structure of interfaces in superconducting/ferromagnetic YBa₂Cu₃O_7−x/La_0.67Ca_0.33MnO₃ superlattices has been analyzed by scanning transmission electron microscopy and high spatial resolution electron energy loss spectroscopy. Individual layers are flat over long lateral distances. The interfaces are coherent, free of defects, exhibiting no roughness, and are located at the BaO plane of the superconductor. Concerning chemical disorder, EELS measurements show the absence of measurable chemical interdiffusion within experimental error bars.     

插层Al2O3对氧化铪基忆阻器的性能优化及多值特性研究

近年来,氧化铪基忆阻器因其优异的阻变性能及与CMOS工艺兼容等特点而被广泛研究。然而,氧化铪基忆阻器仍存在以下问题:1) 器件良率、可靠性、均一性不足;2) Set和Reset 过程中电流突变,导致多值特性较差。为实现氧化铪基忆阻器的性能优化及多值特性,文章在HfO₂表面生长一层1~5 nm Al₂O₃,构造Al₂O₃/HfO₂双介质层忆阻器,并对HfO₂和Al₂O₃的厚度进行优化,最终得到性能显著提升的Al₂O₃/HfO₂双介质层多值忆阻器。该器件呈现出保持性良好的10个不同电阻态(1×10⁴ s@85℃)。由于氧离子在Al₂O₃层的迁移率更低,限制了氧空位细丝生长速率及宽度,且Al₂O₃具有热增强作用,使氧空位分布更均匀,促使氧空位细丝生成/断裂过程由突变转为渐变。该工作为进一步实现氧化铪基忆阻器的性能优化及多值特性提供了参考。     

Drain current enhancement and negligible current collapse in GaN MOSFETs with atomic-layer-deposited HfO2 as a gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect-transistors (MOSFET’s) with atomic-layer-deposited HfO₂ gate dielectrics have been fabricated; a 4 μm gate-length device with a gate dielectric of 14.8 nm in thickness (an equivalent SiO₂ thickness of 3.8 nm) gave a drain current of 230 mA/mm and a broad maximum transconductance of 31 mS/mm. Owing to a low interfacial density of states (D_it) at the HfO₂/GaN interface, more than two third of the drain currents come from accumulation, in contrast to those of Schottky-gate GaN devices. The device also showed negligible current collapse in a wide range of bias voltages, again due to the low D_it, which effectively passivate the surface states located in the gate-drain access region. Moreover, the device demonstrated a larger forward gate bias of +6 V with a much lower gate leakage current.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

Interface optimization using diindenoperylene for C60 thin film transistors with high electron mobility and stability

C₆₀-based organic thin film transistors (OTFTs) with high electron mobility and high operational stability are achieved with (1 1 1) oriented C₆₀ films grown by using template effects of diindenoperylene (DIP) under layer on the SiO₂ gate insulator. The electron mobility of the C₆₀ transistor is significantly increased from 0.21 cm² V⁻¹ s⁻¹ to 2.92 cm² V⁻¹ s⁻¹ by inserting the template-DIP layer. Moreover much higher operational stability is also observed for the DIP-template C₆₀ OTFTs. A grazing incidence X-ray diffraction and ultrahigh-sensitivity photoelectron spectroscopy measurements indicate that the improved electron mobility and stability arise from the decreased density of trap states in the C₆₀ film due to increased (1 1 1) orientation of C₆₀-grains and their crystallinity on the DIP template.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

一氧化氮退火对高温氧化SiC/SiO2界面特性的影响研究

本文研究了高温（1300℃）氧化并在一氧化氮（NO）气体中进行氧化后退火方法对4H-SiC 金属-氧化物-半导体（MOS）电容的SiC/SiO2界面特性的影响,主要通过SiC MOS的电容-电压(C-V)特性详细讨论了NO退火时间和温度与SiO2/SiC界面特性的相互关系. 结果表明在NO气体中进行氧化后退火可明显降低界面态密度,并且界面态密度随着温度和时间的增加会进一步降低。 同时,与常规1200℃及以下氧化温度相比,1300℃下热生长的氧化层具有更低的界面态密度且显著缩短了氧化时间,节约了生产成本。     

低温退火对具有HfO2/TiN栅结构的MOS电容电学性能的影响

The effects of low temperature annealing,such as post high-k dielectric deposition annealing(PDA),post metal annealing(PMA)and forming gas annealing(FGA)on the electrical characteristics of a metal–oxide–semiconductor(MOS)capacitor with a TiN metal gate and a HfO2dielectric are systematically investigated.It can be found that the low temperature annealing can improve the capacitance–voltage hysteresis performance significantly at the cost of increasing gate leakage current.Moreover,FGA could effectively decrease the interfacial state density and oxygen vacancy density,and PDA could make the flat band positively shift which is suitable for P-type MOSs.     

Comparison of p–n junction formed by BF2 and B implantation in silicon microstrip detector with low and high thermal budget: impact of fluorine on electrical characteristics

The influence of crystal damage on the electrical properties and the doping profile of the implanted p⁺–n junction has been studied at different annealing temperatures using process simulator TMA-SUPREM4. This was done by carrying out two different implantations; one with implantation dose of 10¹⁵ BF₂⁺ ions/cm² at an energy of 80 keV and other with 10¹⁵ B⁺ ions/cm² at 17.93 keV. Substrate orientation 1 1 1 of phosphorus-doped n-type Si wafers of resistivity 4 kΩ cm and tilt 7° was used, and isochronally annealing was performed in N₂ ambient for 180 min in temperature range between 400°C and 1350°C. The diode properties were analysed in terms of junction depth, sheet resistance. It has been found that for low thermal budget annealing, boron diffusion depth is insensitive to the variation in annealing temperature for BF₂⁺-implanted devices, whereas, boron diffusion depth increases continuously for B⁺-implanted devices. In BF₂⁺-implanted devices, fluorine diffusion improves the breakdown voltage of the silicon microstrip detector for annealing temperature upto 900°C.For high thermal budget annealing, it has been shown that the electrical characteristics of BF₂⁺-implanted devices is similar to that obtained in B⁺-implanted devices.