A bipolar output voltage pulse transformer boost converter with charge pump assisted shunt regulator for thermoelectric energy harvesting

This system presents an energy harvesting system that generates bipolar output voltage (±1 V) based on a miniature 1:1 turn-ratio pulse transformer boost converter using sub-threshold level input voltage source. A shunt regulator is designed using six-transistor Schmitt-Trigger core to limit the boost converter output voltage. Another power stage, i.e. a fully integrated on-chip single-stage cross-coupled charge pump, then generates 3 V output from the unused extra output power of boost converter, which is shunted otherwise. The increased voltage headroom generated is instrumental for sensor, analog and RF circuits. Charge pump clock frequency is designed to adaptively tracking the input voltage, which is sensed using power-saving time-domain digital technique. Based on a standard CMOS 0.13-µm technology, chip measurement verified the operations of the boost converter, shunt regulator and bipolar charge pump prototypes, respectively. Simulations confirmed the full system operations. During start-up, the system only requires minimum start-up input voltage of 36 mV at input power of 5.8 µW.     

∑-Δ ADC在软件无线电移动终端中的应用

模数转换器是基于软件无线电的多模移动终端中的关键器件。∑-Δ模数转换器(∑-ΔADC)是利用∑-Δ调制技术和数字滤波技术实现的一种高精度模数转换器,主要由∑-Δ调制器和数字降采样滤波器构成。简要描述了移动通信信号特征,对闪烁型模数转换器(Flash-ADC)和∑-Δ模数转换器的性能进行了详细分析与比较,指出∑-Δ模数转换器可以更好地满足多模移动终端中对大动态范围A/D转换的要求。     

A stereo asynchronous digital sample-rate converter for digitalaudio

The design of an asynchronous digital sample-rate converter for digital-audio applications is presented. The theory of asynchronous sample-rate conversion is discussed using a signal-processing model that is based on highly interpolated input samples. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the correct polyphase filter for each output sample. Sample-rate ratio changes of up to 2:1 in either direction can be accommodated. The proposed signal-processing algorithm has been implemented in a 0.8-μm CMOS technology. Measurement results show excellent agreement with theory     

A New Design Methodology for Time-Based Capacitance-to-Digital Converters (T-CDCs)

This paper introduces a 9-bit time-based capacitance-to-digital converter (T-CDC). This T-CDC adopts a new design methodology for parasitic cancellation with a simple calibration technique. In T-CDCs, the input sensor capacitance is first converted into a delay pulse using a capacitance-to-time converter (CTC) circuit; then this delay signal is converted into a digital code through a time-to-digital converter (TDC) circuit. A prototype of the proposed T-CDC is implemented in UMC 0.13 μm CMOS technology. This T-CDC consumes 8.42 μW and achieves a maximum SNR of 45.14 dB with a conversion time of 1 μs that corresponds to a figure of merit (FoM) of 16.4 fJ/Conv.     

Detailed analysis of the effect of a hysteretic quantizer in a multibit, Sigma-Delta modulator

A detailed analysis of the impact of a hysteretic quantizer on a multibit, Sigma-Delta modulator has been carried out in this paper. Both discrete-time and continuous-time modulators have been considered. A qualitative modeling of the hysteretic quantizer based on a hysteretic block followed by an ideal quantizer was proposed. Due to the hysteresis effect, the quantizer output signal is delayed and distorted with respect to the quantizer input signal, where the delay causes a phase-shift independent on the signal frequency. Yet, the effect of the hysteresis depends on the input signal amplitude. This model was validated by using system-level simulations for a second order, 3-bit, discrete-time Sigma-Delta modulator. A linear model for hysteresis was derived by assuming a narrow hysteresis cycle. The quantizer input signal plays a fundamental role in the discussion. In order to include this signal into the linear analysis some approximations are proposed. The quantizer output signal is decomposed by the use of the Fourier series analysis only into the in-phase and quadrature components (with respect to the input signal) whose Fourier series coefficients can be analytically calculated. A quantitative analysis for both a second order, 3-bit, DT and CT Sigma-Delta modulators including a hysteretic quantizer was carried out. For the CT modulator, finite GBW in amplifiers, excess loop delay, and a hysteretic quantizer were considered separately and combined. A good agreement with both system-level simulations and experimental results is found, despite the approximations considered for the quantizer input signal.     

Digital noise-shaping of residues in dual-quantization sigma-delta modulators

A new dual-quantization Sigma-Delta modulator is proposed in this paper where the coarse-quantizer output, obtained from the fine-quantizer output by means of a digital noise-shaping coder, is fed back to the input of the first integrator by means of a p-bit digital-to-analog converter (DAC) (typically, p=1). To avoid the truncation error inserted into the first integrator to propagate to the rest of integrators, the residue of the digital coder is first integrated and then fed to the second integrator through an additional multibit DAC. Unlike other dual-quantization architectures, the proposed one allows to obtain a large signal-to-noise plus distortion ratio by using aggressive noise transfer functions, like in conventional multibit modulators. Mismatch effects on performances are carefully analyzed. It will be shown that more than one digital coder can be included in the architecture in order to reduce the number of bits of the additional DAC. Simulation results are presented which support the theoretical analysis.     

数字音频D类功放电源误差校正方法研究

为了实时校正供电电源噪声引起的数字音频D类功放输出误差,提出一种基于FPGA的电源误差校正方法。使用高精度ADC芯片将电源纹波信号转化为数字量后送入FPGA,校正模块根据电源纹波的大小对数字音频D类功放Sigma-Delta调制器输入值进行预校正处理,从而实现在功放输出端有效的抑制电源噪声。经过实际电路测试,该方法可以有效的抑制电源噪声对数字音频D类功放的影响,电源抑制比达到36.78 dB。     

Combined Linear and $Delta$-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters

A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed in a 0.25 mum CMOS process. The modulator employs a DeltaM switch-mode DC-DC buck converter to enhance the efficiency of a linear regulator at backed-off supply voltages and powers. The delta-modulator's noise-shaping characteristic, linear regulator's power supply rejection, digital pre-emphasis of the input envelope, and a closed-loop amplitude path from the PA output are simultaneously used to achieve state-of-the-art modulator performance. The presented supply modulator follows the input signal's envelope with 20 dB output dynamic range, maximum efficiency of 75.5% at an output power of 30.8 dBm, and 75 dB SFDR for envelope signals up to 4 MHz occupied RF bandwidth. For a 1625 kb/s 8 PSK RF input signal at 900 MHz, polar modulation of a commercial low-power GSM-900 PA provides 10 dB ACPR improvement.     

Noise Transfer Characteristics in a Semiconductor Optical Amplifier With Application to Wavelength Conversion Based on a Delay Interferometer

A theoretical model is presented to analyze the noise transfer characteristics in a semiconductor optical amplifier (SOA) under the excitation of a noisy pump signal and a noise-free probe signal. An analytical expression is derived for the optical signal-to-noise ratio (OSNR) of the output probe signal from the SOA. The influence of the gain saturation of the SOA, and the pump and probe signal powers on the noise transfer characteristics is investigated. The noise transfer model is used to determine the output noise power of a delay interference wavelength converter. An analytical expression is obtained for the nonlinear phase change in the SOA, which determines the output power of the wavelength-converted signal. These results show that the noise transfer in the wavelength conversion can be suppressed by increasing the probe signal power, but that the improvement in the output signal OSNR relative to the input signal OSNR is accompanied by a reduction in the conversion efficiency. This fundamental tradeoff can be readily investigated during the design optimization process using the concise results derived in this paper.     

12位Sigma-Delta模数转换器的降采样滤波器设计

一种由SNR（信噪比）驱动的滤波器设计,用于12位Sigma-Delta模数转换器。Sigma-Delta模数转换器包括Sigma-Delta调制器和降采样滤波器两部分,首先用Sigma-Delta调制器对信号进行过采样率量化,然后通过降采样滤波器进行数字信号处理,将信号还原到原始采样率并去除量化噪声。和传统的模数转换器相比,Sigma-Delta模数转换器具有采样率高、精度高、面积小等优点。Sigma-Delta模数转换器的滤波器设计有降采样率和滤波性能两个指标要求,该设计方法由SNR驱动并采用了两种滤波器方案,设计结果在MATLAB里进行了仿真,其SNR大于74 dB,达到12位Sigma-Delta模数转换器的要求。     

光学Sigma-Delta模数转换器的研究进展

采用光学模数转换技术已经成为高转换速率、高比特精度模数转换器(ADC)的发展趋势.光学Sigma-Delta ADC作为一种光学ADC,具有转换精度高和模拟电路简单等显著优点.介绍了光学Sigma-Delta ADC的基本原理,详细阐述了几种典型的光学Sigma-Delta ADC的系统结构,对不同结构的光学Sigma-Delta ADC的优缺点进行了归纳总结.     

A 0.9 V 96 μW Fully Operational Digital Hearing Aid Chip

A 0.9 V 96 muW fully operational low-power digital hearing aid chip is proposed and implemented. An internal status controller is introduced to achieve full operation of the adaptive-SNR analog front end. Dedicated DSP with an additional volume control parameter eliminates any internal overflow and enables the hearing aid to be customized for each individual user. When the input audio band is split into a low band and a high band, the audio signal can be processed coarsely. In addition, fine processing of the high-band signal can be obtained with a low-power automatic gain control (AGC) comprising a digital comparator and a subtraction unit. A heterogeneous Sigma-Delta DAC reduces the power consumption of the interpolation filter without degrading performance by allowing different frequencies between the input signal and the sampling clock of the Sigma-Delta modulator. Compared with a conventional Sigma-Delta DAC, the heterogeneous Sigma-Delta DAC reduces the power dissipation by 40.4% and the area occupation by 40.5%, and it has a reported error rate of only 0.16%. The fabricated chip achieves a 79 dB peak SNR with 4.1 muVrms of input-referred noise voltage. The core area is 2.8 mm x 1.1 mm in a 0.18 mum standard CMOS process.     

New Σ-Δ Voltage to Frequency Converter Analysis and Applications

Voltage to frequency converter (VFC) is an oscillator whose frequency is linearly proportional to control voltage. There are two common VFC architectures: the current steering multivibrator and the charge-balance VFC. For higher linearity, the charge-balancing method is preferred. The charge balanced VFC may be made in asynchronous or synchronous (clocked) forms. The synchronous charge balanced VFC or “sigma delta” Sigma-Delta VFC (SVFC) is used when output pulses are synchronized to a clock. The charge balance VFC is more complex, more demanding in its supply voltage and current requirements, and more accurate. It is capable of 16 to18 bit linearity. In this paper, the new SVFC (NSVFC) is described. This NSVFC works similarly as conventional SVFC but it has a pure tone on output (for constant input voltage). Therefore, it is possible to measure the period of NSVFC output (this does not work for SVFC). Milan Stork received the M.Sc. degree in electrical engineering from the Technical University of Plzen, Czech Republic at the department of electronics in 1974 and Ph.D. degree in automatic control systems at the Czech Technical University in Prague in 1985. In 1997, he became as Associate Professor at the Department of Applied Electronics and Telecommunication, faculty of electrical engineering on University of West Bohemia in Plzen, Czech Republic. He has numerous journal and conference publications. He is member of editorial board magazine “Physician and Technology”. His research interest include analog/digital systems, signal processing and biomedical engineering, especially cardiopulmonary stress tests systems.     

A 62.5–625-MHz Anti-Reset All-Digital Delay-Locked Loop

An anti-reset all-digital delay-locked loop (DLL) is presented. When the input clock frequency changes significantly, the dynamic frequency detector re-locks the DLL without any external reset signal. The proposed binary time-to-digital converter (BTDC) reduces effectively the hardware, compared with a conventional TDC. Unlike many previous all-digital DLLs, this one is a closed feedback loop that can track environmental variations. The input frequency range can be operated from 62.5-625 MHz. It spends at most six cycles to synchronize the input and output clocks.     

Robust Multiple-Phase Switched-Capacitor DC–DC Power Converter With Digital Interleaving Regulation Scheme

An integrated switched-capacitor (SC) DC–DC converter with a digital interleaving regulation scheme is presented. By interleaving the newly-structured charge pump (CP) sub-cells in multiple phases, the input current ripple and output voltage ripple of the converter are reduced significantly. The converter exhibits excellent robustness, even when one CP sub-cell fails to operate due to unexpected device failure. A fully digital controller is employed with hysteretic control, featuring deadbeat stability and fast transient response. With a 1.5-V input power supply, the SC power converter precisely provides an adaptable regulated power output from 1.6 to 2.7 V. A maximum output ripple of $pm $20 mV is observed at the full load of 540 mW. The load transient response is around 1.8 $mu$s, when the load current switches from half to full load (from 100 to 200 mA). The design provides a fast-response, low-noise, and fault-tolerant solution to new-generation on-chip power supplies.      

Review and advances in delta-sigma DAC error estimation based on additive noise modelling

High-resolution and very high resolution data conversion is dominated by the use of delta-sigma modulating converters. Oversampling and noise-shaping is employed to enable a coarsely quantized conversion with high effective resolution. The time-domain output waveform from a delta-sigma modulator is often impossible to predict analytically, therefore modulator design is largely based on high level digital simulations and rule-of-thumb estimation. However, the output waveform also largely determines the distortion caused by analog error sources in the converter. Therefore optimization of the modulator with regards to digital quantization noise might not yield an optimal design when analog errors are included. This paper extends common estimation methods to include analog error sources, with the objective of enabling more global rule-of-thumb optimization.     

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.     

Polarization insensitive frequency converter with the capability ofchirp removal

We report on a new type of polarization insensitive frequency conversion technique using four-wave mixing (FWM) in a semiconductor optical amplifier (SOA). In this technique the input signal is spectrally duplicated by a Mach-Zehnder type phase modulator. Then, the resulting two waves generate the frequency converted output signal by FWM with use of an additional pump wave. The converted output wavelength is independent of the wavelength of the input signal. In addition to the frequency conversion, the chirp of the input signal is removed by the FWM process bit-error-rate (BER)-measurements after transmission of the converted signal over standard communication fiber are reported     

All-Digital PLL With Ultra Fast Settling

A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator with sufficiently fine frequency resolution to avoid analog tuning. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. When implemented in highly scaled digital CMOS processes, the proposed architecture is more advantageous over conventional charge-pump-based phase-locked loops (PLLs) since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. In this brief, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception. This approach has been validated and incorporated in commercial single-chip Bluetooth and Global System for Mobile Communications radios realized in deep-submicrometer CMOS     

基于光纤光栅外腔半导体激光器增益饱和效应的全光波长转换实验研究

对基于光纤光栅外腔半导体激光器增益饱和效应的全光波长转换器的静态与动态特性进行了实验研究。为消除反馈光与转换信号输出光对光源的不利影响及提高光输入、输出信号耦合效率 ,提出了采用环形器进行信号耦合的光学结构。实验结果表明 ,转换器件具有高于 30nm的波长转换间隔 ,并可实现波长上、下转换。进行了15 5Mbit/s伪随机码调制信号的动态波长转换实验。