Plasma-induced micro breakdown in small-area MOSFETs

We investigated the impact of latent plasma-induced damage (PID) on the reliability of nMOSFETs with small gate area and gate-oxide thickness of 3.2 nm. To this purpose, we stressed 1500 devices with different antenna areas by using a staircase-like stress voltage and by monitoring the gate leakage at the gate voltage V/sub G/=+2 V. The stress was always stopped because of an abrupt jump in the gate current. The statistics obtained for the breakdown current are characterized by two different oxide-breakdown modes. The first is the well-known hard breakdown (HB), while the second one, which we called micro breakdown (MB), can be modeled as a double trap-assisted tunneling (D-TAT) mechanism and is characterized by a very small leakage current (around 100 pA at the gate voltage V/sub G/=2 V). In devices with large antenna, i.e., more prone to be damaged by plasma processing, the number of microbroken oxides is larger and breakdown occurs at lower voltages than in reference devices (non plasma damaged). Conversely, the hard breakdown statistics shows only a weak dependence on the gate antenna ratio of plasma damaged devices. This has been explained by considering the intrinsic nature of latent plasma-induced oxide defects, linked to the different generation mechanisms involved in micro breakdown and hard breakdown phenomena.     

Stress distribution on [100] Si wafer mapped by novel I-V analysis of MOS tunneling diodes

The current-voltage (I-V) characteristics of metal-oxide-semiconductor tunneling diodes distributed over a 3-in Si wafer were analyzed to investigate the stress distribution on the wafer. Generally, the substrate injection saturation current (J/sub sat/) decreases as the gate injection leakage current (J/sub g/) increases, the latter being dominated by oxide thickness via a trap related mechanism. A universal curve to fit all analyzed data was found and it is suggested that devices with extremely high (low) J/sub sat/ at a given J/sub g/ should be located in areas of the silicon lattice with relatively high external compressive (tensile) stress because of the stress-induced bandgap variation effect. The mapped locations of the highly stressed devices on a 3-in [100] Si wafer correspond to the patterns of slips caused by thermal stress during rapid thermal processing, as described in previous reports.     

Localized oxide degradation in ultrathin gate dielectric and its statistical analysis

Conventional oxide reliability studies determine oxide lifetime by measuring the time to breakdown or quasi-breakdown (QB). In ultrathin gate oxides with T/sub ox/<14 /spl Aring/, however, it is hard to observe breakdown or QB under typical stress conditions. Instead, the gate leakage current shows a continuous increase over the entire time period of electrical stress. As the magnitude of the gate current density increase eventually becomes too high to be acceptable for normal device operation, a lifetime criterion based on the increase in gate leakage current is proposed. Our paper also shows that the area-dependence of the gate leakage current density increase in 13.4 /spl Aring/ oxides is different from that in thicker oxide films, indicating a localized and discrete property of the leakage current. It has also been observed that the oxide lifetime based on the new lifetime criterion is shorter when the gate area is smaller, as opposed to the conventional area dependence of time-to-breakdown test. A simple model consisting of multiple degraded spots is proposed and it has been shown that localized gate leakage current can be described by Weibull's statistics for multiple degraded spots.     

Hf-doped and NH/sub 3/-nitrided high-K gate dielectric thin film with least drain current degradation and flatband voltage shift

A novel technique to form high-K dielectric of HfSiON by doping base oxide with Hf and nitridation with NH/sub 3/, sequentially, is proposed. The HfSiON gate dielectric demonstrates excellent device performances such as only 10% degradation of saturation drain current and almost 45 times of magnitude reduction in gate leakage compared with conventional SiO/sub 2/ gate at the approximately same equivalent oxide thickness. Additionally, negligible flatband voltage shift is achieved with this technique. Time-dependent dielectric breakdown tests indicate that the lifetime of HfSiON is longer than 10 years at V/sub dd/=2 V.     

Effects of ionizing radiation on n-channel MOSFET's fabricated in zone-melting-recrystallized Si films on SiO2

We have investigated the effects of irradiation with 1.5 MeV electrons on the electrical characteristics of n-channel MOSFET's fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates. With a -15 V bias applied to the Si substrate during irradiation and device operation, the subthreshold leakage current remains below 0.2 pA/µm (channel width) for ionizing doses up to 10⁶rad(Si). The negative substrate bias also reduces the shift of threshold voltage to less than 0.3 V for devices with 50 nm-thick gate oxide.     

The influence of p-polysilicon gate doping on the dielectric breakdown of PMOS devices

The influence of the gate electrode p-polysilicon doping concentration on gate oxide breakdown data is investigated. It is shown that a small variation in doping concentration of p-doped polysilicon gates as well as an inversion layer in p-polysilicon gate strongly affects the results, if PMOS devices are stressed in inversion biasing mode by applying a constant current stress.     

Gate oxide leakage due to temperature accelerated degradation under plasma charging conditions

Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices.     

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.     

Effect of FN stress and gate-oxide breakdown on high-frequency noise characteristics in deep-submicrometer nMOSFETs

The impact of Fowler-Nordheim (FN) stress and oxide breakdown on high-frequency noise characteristics in 0.18 /spl mu/m nMOSFET has studied. Noise characteristics of the devices at different leakage levels and breakdown hardness are compared. The results have shown a strong dependence of degradation of noise parameter on the gate leakage. The degradation mechanisms are analyzed by extraction of the channel and gate noise using a noise equivalent circuit model. It has been found that gate shot noise, which is commonly ignored in the as-processed nMOSFET, plays a dominant role in determining the high frequency noise in the post-oxide breakdown nMOSFET. The effect of FN stress and oxide breakdown is negligible.     

High-performance RSD poly-Si TFTs with a new ONO gate dielectric

This paper developed a novel polycrystalline silicon (poly-Si) thin-film transistor (TFT) structure with the following special features: 1) a new oxide-nitride-oxynitride (ONO) multilayer gate dielectric to reduce leakage current, improved breakdown characteristics, and enhanced reliability; and 2) raised source/drain (RSD) structure to reduce series resistance. These features were used to fabricate high-performance RSD-TFTs with ONO gate dielectric. The ONO gate dielectric on poly-Si films shows a very high breakdown field of 9.4 MV/cm, a longer time dependent dielectric breakdown, larger Q/sub BD/, and a lower charge-trapping rate than single-layer plasma-enhanced chemical vapor deposition tetraethooxysilane oxide or nitride. The fabricated RSD-TFTs with ONO gate dielectric exhibited excellent transfer characteristics, high field-effect mobility of 320 cm/sup 2//V/spl middot/s, and an on/off current ratio exceeding 10/sup 8/.     

Oxide reliability of drain engineered I/O NMOS from hot carrier injection

The impact of hot carrier stress on the breakdown properties of I/O NMOS gate oxide is reported. I/O NMOS devices with drain structures using standard LDD with pocket (S-LDD) and graded LDD without pocket (G-LDD) are used. Time-dependent (TDDB) and voltage-ramp (VRDB) dielectric breakdown tests are performed for devices with and without hot-carrier-injection. It is demonstrated that both I/O structures show similar oxide integrity after hot carrier injection (HCI) when the Idsat degradation is small (<5%), but show significantly different oxide lifetimes when the Idsat degradation is high (>5%). At 10% I/sub dsat/ degradation, the oxide lifetime for the G-LDD structure is reduced by about a factor of 10 compared to that of the S-LDD structure. The correlation between oxide integrity and leakage current indicates that the oxide charge introduced by HCI stress is the reason for oxide degradation. This work clearly demonstrates that the effect of hot carrier induced oxide damage must be included when predicting the oxide lifetimes of advanced I/O NMOS devices.     

New insights on the post-BD conduction of MOS devices at the nanoscale

We have combined standard electrical tests with conductive-atomic force microscopy experiments to investigate the conduction of MOS devices after the dielectric breakdown (BD) of the SiO/sub 2/ gate oxide. In particular, the influence of the conduction nanometer scale parameters on the overall device post-BD current-voltage characteristics has been analyzed. The results show a nonuniform conductivity of the oxide at the BD area and that the total current flowing through the device is mainly driven by a very small fraction of that region.     

Double-implanted subvolt JFETs

The fabrication and performance characteristics of double-implanted subvolt pinchoff JFETs suitable for low-voltage micropower analog applications are described. The process requires the addition of only one mask to the standard bipolar process. Typical devices exhibit a breakdown voltage of 5.5 V, gate leakage in the low pA range, a pinchoff voltage of about 0.5 V and a cutoff frequency of 10.4 MHz.     

Limitation of spacer thickness in titanium salicide ULSI CMOStechnology

The isolation integrity of various gate-spacer thicknesses in 15-20-μm-wide MOS devices with and without titanium salicide is discussed. The gate-spacer thickness varies from 25 to 100 nm. Experimental results show that for Ti salicided devices with only a 25-nm-thick gate spacer, a broad spectrum of gate-drain (source) breakdown voltages, at a leakage current level of 2 μA, is measured in the range of 1.5 to 10 V. Using a specific gate-spacer tester with a total gate-spacer perimeter near 10 cm in length, the statistical data taken over 100 tested chips show that as the thickness of the gate spacer is reduced to less than 50 nm, the gate leakage increases to 10 ^-9 A under a gate bias equal to 5 V. The leakage of the thin gate spacer is attributed to the formation of Ti-rich oxide during the Ti self-aligned silicide process, which degrades the isolation integrity and generates a leakage path. The implications of this leakage mechanism for ULSI technologies are discussed     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

Subbreakdown drain leakage current in MOSFET

Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero VGin thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.     

Electrical characterization and material evaluation of zirconium oxynitride gate dielectric in TaN-gated NMOSFETs with high-temperature forming gas annealing

The electrical, material, and reliability characteristics of zirconium oxynitride (Zr-oxynitride) gate dielectrics were evaluated. The nitrogen (/spl sim/1.7%) in Zr-oxynitride was primarily located at the Zr-oxynitride/Si interface and helped to preserve the composition of the nitrogen-doped Zr-silicate interfacial layer (IL) during annealing as compared to the ZrO/sub 2/ IL - resulting in improved thermal stability of the Zr-oxynitride. In addition, the Zr-oxynitride demonstrated a higher crystallization temperature (/spl sim/600/spl deg/C) as compared to ZrO/sub 2/ (/spl sim/400/spl deg/C). Reliability characterization was performed after TaN-gated nMOSFET fabrication of Zr-oxynitride and ZrO/sub 2/ devices with equivalent oxide thickness (EOTs) of 10.3 /spl Aring/ and 13.8 /spl Aring/, respectively. Time-zero dielectric breakdown and time-dependent dielectric breakdown (TDDB) characteristics revealed higher dielectric strength and effective breakdown field for the Zr-oxynitride. High-temperature forming gas (HTFG) annealing on TaN/Zr-oxynitride nMOSFETs with an EOT of 11.6 /spl Aring/ demonstrated reduced D/sub it/, which resulted in reduced swing (69 mV/decade), reduced off-state leakage current, higher transconductance, and higher mobility. The peak mobility was increased by almost fourfold from 97 cm/sup 2//V/spl middot/s to 383 cm/sup 2//V/spl middot/s after 600/spl deg/C HTFG annealing.     

超薄栅氧化物pMOSFET器件在软击穿后的特性

研究了在软击穿后MOS晶体管特性的退化.在晶体管上加均匀的电压应力直到软击穿发生的过程中监控晶体管的参数.在软击穿后,输出特性和转移特性只有小的改变.在软击穿发生时,漏端的电流和域值电压的退化是连续变化的.但是,在软击穿时栅漏电流突然有大量的增加.对软击穿后的栅漏电流增量的分析表明,软击穿后的电流机制是FN隧穿,这是软击穿引起的氧化物的势垒高度降低造成的.     

超薄栅氧化物pMOSFET器件在软击穿后的特性

研究了在软击穿后MOS晶体管特性的退化.在晶体管上加均匀的电压应力直到软击穿发生的过程中监控晶体管的参数.在软击穿后,输出特性和转移特性只有小的改变.在软击穿发生时,漏端的电流和域值电压的退化是连续变化的.但是,在软击穿时栅漏电流突然有大量的增加.对软击穿后的栅漏电流增量的分析表明,软击穿后的电流机制是FN隧穿,这是软击穿引起的氧化物的势垒高度降低造成的.