CdTe钝化的HgCdTe非平衡载流子表面复合速度的实验研究

利用Ａｒ＾＋束央求宙积技术在ＧｇＣｄＴｅ表面实现了低温ＣｄＴｅ介质薄膜的低温生长。在用－ＨｇＣｄＴｅ晶片表面分别用ＣｄＴｅ介质膜、ＨｇＣｄＴｅ自身阳极氧化膜进行表面钝化。利用光电导衰退测量技术测量了两种不同表面钝化的薄ＨｇＣｄＴｅ晶片的非平衡载流子（少数载流子）寿命,并通过光电导衰减信号波形的拟合,得到两种不同表面钝化的ＨｇＣｄＴｅ表面复合速度。实验结果表明,获得的ＣｄＴｅ／ＨｇＣｄＴｅ界面质量已     

n—HgCdTe光导器件两种表面钝化研究

利用Ａｒ＾＋束溅射沉积技术实现了ＣｄＴｅ薄膜的低温生长,利用电化学方法进行了ＨｇＣｄＴｅ表面自身阳极氧化膜的生长,利用生工的ＣｄＴｅ介质膜和ＨｇＣｄＴｅ表在身阳极氧化膜对ｎ－ＨｇＣｄＴｅ光导器件进行了表面钝化。对两种器件的电阻、各项性能指标进行了测量分析,实验表明得到的ＣｄＴｅ／ＨｇＣｄＴｅ同质量已达到器件实用化水平。     

HgCdTe表面氧化特性

利用Ｘ射线光电子谱对ＨｇＣｄＴｅ表面氧特性进行了研究，对不同工艺过程中的ＨｇＣｄＴｅ表面进行了测量、分析。结果表明ＨｇＣｄＴｅ表面的自生氧化与表现处理工艺密切相关，说明ＨｇＣｄＴｅ表面钝化前的表面预处理直接影响钝纶层／ＨｇＣｄＴｅ的界面特性。     

HgCdTe超重力晶体生长系统原理设计

为了制备组份均匀的ＨｇＣｄＴｅ材料,设计了一种在超重力条件下制备ＨｇＣｄＴｅ材料的晶体生长系统。超重力由离心机产生,ＨｇＣｄＴｅ熔体在超重力条件下产生的重吧用来抵消Ｂｒｉｄｇｍａｎ生长过程中产生的组份分凝,为了获得组份均匀的ＨｇＣｄＴｅ晶体,必需在Ｂｒｉｄｇｍａｎ生长过程中,随剩余熔体长度的变化改变离心机的转速,通过理论推导,求得离心机转速与剩余熔体长度的关系。     

金属有机化合物汽相外延碲镉汞薄膜的进展

回顾了金属有机化合物汽相外延碲镉汞薄膜的发展历程，简要叙述了ＭＯＶＰＥＨｇＣｄＴｅ薄膜的三种主要技术，与ＨｇＣｄＴｅ晶格匹配和失配的衬底材料，各种金属有机物源和掺杂研究的新近进展。还介绍了ＭＯＶＰＥ－ＨｇＣｄＴｅ薄膜和探测器目前达到的水平。大量结果已经表明，ＭＯＶＰＥ生长的ＨｇＣｄＴｅ薄膜的质量适合于制造高质量的光伏型探测器，ＭＯＶＰＥ是一种原位生长先进的ＨｇＣｄＴｅ红外焦平面列阵既实用又富生命力     

碲镉汞薄膜材料

研制ＨｇＣｄＴｅ焦平面器件是当前实现长波红外焦平面器件的主要途径。红外焦平面器件要求大面积、均匀性好和高质量的ＨｇＣｄＴｅ材料。用ＬＰＥ、ＭＯＣＶＤ和ＭＢＥ外延生长的ＨｇＣｄＴｅ薄膜材料可满足焦平面器件对材料的要求。ＬＰＥ是目前研制ＨｇＣｄＴｅ光伏列阵主要材料，用双层掺杂生长的ｐ－ｎ异质结得到当前最高的Ｒ＿０Ａ值。ＭＯＣＶＤ和ＭＢＥ生长的ＨｇＣｄＴｅ外延膜近期有了较大的进展，除了在硅衬底上ＭＢＥ生长ＨｇＣｄＴｅ仍在研究之外，其它已趋向成熟并开始转向工业生产。为了研制高质量的ＨｇＣｄＴｅ外延膜，高质量的衬底材料与建立薄膜均匀性的检测工艺是十分必要的。     

HgCdTe—CdTe异质结构的变频导纳特性

采用宽频带导纳测试系统研究了Ｈｇ０．６６Ｃｄ０．３４Ｔｅ－ＣｄＴｅ异质结构和Ａｌ－半绝缘ＣｄＴｅ－Ｈｇ０．６６Ｃｄ０．３４Ｔｅ结构样品的变频导纳特性，分析了不同结构样吕的测试结果，表明：异质结ＨｇＣｄＴｅ表面空穴积累，ＣｄＴｅ表面空穴耗尽，界面处的势垒使载流子局限于ＨｇＣｄＴｅ体内，样品的光伏响应光谱在２９７０ｃｍ＾－１和３６５０ｃｍ＾－１处各有一个响应峰，前者对应于界面ＨｇＣｄＴｅ的本征光伏效庆     

引晶技术在HgCdTe体单晶生长中的应用

引晶技术在ＨｇＣｄＴｅ体单晶生长中的应用郎维和（华北光电技术研究所北京１０００１５）ＨｇＣｄＴｅ是一种三元化合物，根据其化学配比可以在一定范围内制备各种禁带宽度的半导体光电材料。为了满足多元红外探测器的要求，我们进行引入籽晶技术生长ＨｇＣｄＴｅ晶体，...     

离子束刻蚀光导HgCdTe探测器芯片的温度限制

利用离子对束对光导ＨｇＣｄＴｅ芯片阳极氧化膜，Ｃｒ－Ａｕ电极和ＨｇＣｄＴｅ芯片的成形进行刻蚀，要求ＨｇＣｄＴｅ芯片表面温度不能超过８０℃。     

HgCdTe表面钝化新方法

ＨｇＣｄＴｅ表面钝化新方法龚海梅，李言谨，方家熊（上海技术物理研究所上海２０００８３）本文首次提出了脉冲式阳极氧化生长ＨｇＣｄＴｅ表面钝化膜的方法，自行设计研制成功一种新颖的脉冲式阳极氧化装置，获得了优于传统恒流方式生长的ＨｇＣｄＴｅ阳极氧化膜界面，...     

抑制In元素在CdTe中的退火扩散

分子束外延HgCdTe/InSb 材料需要阻止 In 元素在 HgCdTe 中的不受控扩散。我们使用 CdTe缓冲层作为阻挡层,以期控制 In 的扩散。为研究 In 元素在 CdTe 材料中的扩散,我们使用分子束外延方法获得CdTe/InSb样品。考虑到在退火时In 元素可能通过环境扩散污染材料,我们使用 SiO2 作为钝化层,通过对比试验发现 In 元素通过环境扩散污染表面的证据,为控制 In 元素的扩散提供新的思路。     

MBE外延InSb基CdTe工艺研究

成功制备了CdTe/InSb复合衬底,为长波HgCdTe外延提供了可能。通过工艺研究解决了InSb氧化层去除及In元素扩散控制两个难点问题,使用As钝化法可以解决双腔衬底转移的问题,在常用的退火工艺下,通过厚度的调整可以阻挡In元素的扩散。     

Influence of Hg pressure on diffusion coefficient of As in HgCdTe

Arsenic diffusion coefficients were measured in HgCdTe at 350°C within the single phase field. The diffusion coefficients displayed a strong dependence on Hg pressure, increasing by more than 1×10³ with decreasing Hg pressure. These measurements were performed by growing As doped HgCdTe films by Hg-rich liquid phase epitaxy on undoped or In-doped base layers, where the growth temperature ranged between 330 and 350°C. Use of these low growth temperatures under Hg-rich conditions permitted attainment of virtual step profiles in As, with negligible diffusion into the base layers. These provided ideal starting points for subsequent diffusion anneals. Diffusion of arsenic under selected low Hg pressures was then employed to tune the positioning of the p/n junction for double layer heterojunction films, by locating it ahead of the heterointerface. Formation of valence band barriers to the photogenerated minority carriers across the junction could thus be avoided. When on the other hand, diffusion experiments were performed under Hg saturated conditions, the heterointerface moved at a faster rate than the p/n junction, leading to the formation of valence band barriers.     

长波碲镉汞材料As掺杂激活研究

利用离子注入工艺实现长波碲镉汞材料的As掺杂,As作为掺杂介质表现出两性掺杂行为,而As只有占据Te位成为受主才能形成P型碲镉汞材料。通过对砷掺杂碲镉汞材料在汞气氛中进行退火,分析注入退火引起的样品电学性质的变化,对砷激活退火采用的汞压、温度及时间进行了研究,利用霍尔测试和二次离子质谱仪(SIMS)等手段分析激活效果,研究发现,高温富汞热退火可以实现碲镉汞As激活。     

Si基HgCdTe变面积光伏探测器的变温特性研究

通过变面积Si基HgCdTe器件变温I-V测试和暗电流特性拟合分析,研究了不同偏压下n-on-p型Si基HgCdTe光伏器件的暗电流成分与Si基HgCdTe材料少子扩散长度和少子寿命随温度的变化规律.在液氮温度下,随着反向偏压的增大器件的表面漏电流在暗电流中所占比重逐渐增加.在零偏压下,当温度低于200 K时材料的少子...     

Modeling of Copper SIMS Profiles in Thin HgCdTe

Anomalous secondary-ion mass spectroscopy (SIMS) profiles of copper in thin pieces of HgCdTe are explained using the model used for diode formation by ion milling and ion implantation. In this model, the SIMS ion beam injects mercury interstitials into the HgCdTe as it etches the HgCdTe. The interstitials fill metal vacancies and kick copper off the metal lattice sites. The copper interstitials then diffuse either to the surface being etched, where it is removed and detected by the SIMS instrument, or deeper into the HgCdTe, where it annihilates vacancies. Good agreement between model predictions and experimental SIMS profiles are obtained.     

Enhanced arsenic diffusion and activation in HgCdTe

Temperature and time dependent Hg-annealing studies for arsenic activation have been carried out on As-doped molecular beam epitaxy HgCdTe eitherin situ or by ion implantation to determine the extent of arsenic activation in the single layer. Enhanced As diffusion and activation in double layer heterostructures have also been investigated to further our understanding of the effects on zero bias resistance-area product (R_oA) and quantum efficiency. The results show that the arsenic activation anneal is limited by Hg self-diffusion into the HgCdTe epilayer. Using this arsenic activation process for eitherin situ doped arsenic or implanted arsenic, high performance p-on-n double layer heterostructure photodiodes have been demonstrated on both mesa and planar device structures.     

甚长波碲镉汞探测器的注入区扩散研究

在碲镉汞甚长波320×256探测器上制备了不同注入区光刻尺寸的区域,通过对不同区域的信号及注入光刻尺寸的关系进行分析对比和数据拟合,获得了不同温度下的扩散距离和单位有效光敏面积在单位时间的响应电压,对于碲镉汞甚长波探测器的器件版图设计和性能提升提供了可靠的数据支撑。     

Annealing effect on the P-type carrier concentration in low-temperature processed arsenic-doped HgCdTe

We report the results of annealing effects on the As-doped alloy HgCdTe grown by molecular beam epitaxy (MBE), arsenic (As) diffusion in HgCdTe from Hg-rich solutions at low temperatures, and As ion implantation at room temperature. Hall-effect measurements, secondary ion mass spectrometry and p-on-n test photodiodes were used to characterize the As activation. High As-doping levels (10¹⁷−10¹⁹ cm⁻³) could be obtained using either MBE growth, As diffusion or As ion-implantation. Annealed below 400°C, As doping in HgCdTe shows n-type characteristics, but above 410°C demonstrates that all methods of As doping exhibit p-type characteristics independent of As incorporation techniques. For example, for samples annealed at 436°C (P_Hg≈2 atm), in addition to p-type activation, we observe a significant improvement of p/n junction characteristics independent of the As source; i.e. As doping either in situ, by diffusion, or ion implantation. A study of this As activation of As-doped MBE HgCdTe as a function of anneal temperature reveals a striking similarity to results observed for As diffusion into HgCdTe and implanted As activation as a function of temperature. The observed dependence of As activation on partial pressure of Hg at various temperatures in the range of 250 to 450°C suggests that As acts as an acceptor at high Hg pressure (>1 atm) and as a donor at low Hg pressure (<1 atm) even under Hg-rich conditions.     

Negative diffusion capacitance in auger-Suppressed HgCdTe heterostructure diodes

An ac analytical model of the diffusion capacitance properties of a pπn HgCdTe heterostructure extracting diode is developed. The results show that the diffusion capacitance dominates the impedance, and can be negative, depending on the length of the intrinsic region. Experimental results on typical diodes show a capacitance of the magnitude predicted, but with a rather more complex frequency dependence, with two changes in sign in the frequency range 20 Hz-1 MHz. The existence of a negative capacitance region is not found to be dependent on the existence of a negative resistance region. The discrepancy between theory and experiment is ascribed to the existence of charge trapping. The results are also discussed in terms of time domain variation of a small perturbation current. The results for the capacitance at high frequency are used to predict the high frequency performance limit of such devices.