键合集成AlGaInP/GaAs/InGaAsP/InGaAs太阳电池组分与厚度对效率的影响

寻找比传统晶格匹配GaInP/InGaAs/Ge结构具有很高效率的高效太阳电池体系是目前高效太阳电池研究重点。基于直接键合集成技术的AlzGa1-zInP/GaAs/In1-xGaxAsyP1-y/InGaAs四结太阳电池是一条有效的途径。该结构中In-GaAsP材料光学带隙可以在0.75～1.35 eV之间连续调节。作为一种新结构,一些关键点还是不清楚,比如考虑材料吸收系数与实际厚度限制下的带隙优化组合,子电池厚度与最高效率之间的耦合影响等,这些都对结构设计提出了新的挑战。采用半经验全局优化工具,研究了InGaAsP子电池组分和吸收系数比较小的InGaAs子电池厚度这两个因素对最高效率的影响,并对器件设计给出了一些方向性意见。     

空间用高效激光电池研究

激光电池在空间无线能量传输领域有很大的应用前景，适合在空间无线传输中，作为能量接收器或信号接收器使用。根据空间应用场景，研制了针对808 nm波段激光的纵向串联2结薄膜激光电池。单体激光电池开路电压达到2.29 V，光电转换效率最高可达52%，电池面密度为0.03 g/cm²。为进一步提升技术成熟度，满足空间实际应用，设计了内级联结构的下一代高效激光电池。该激光电池采用半导体异质集成工艺的金属图形键合技术，为横向纵向混合串联8结结构，预计单体激光电池开路电压超过8 V，光电转换效率突破55%。     

燃料电池电动汽车关键技术探究

燃料电池汽车作为高效清洁的电动汽车,相对于传统的内燃机汽车,动力传动系统采用电动机替代了内燃机成为燃料电池汽车的动力源。介绍了燃料电池汽车技术发展概况,围绕燃料电池电动汽车动力传动系统、整车集成技术和仿真优化技术等关键技术开展了详细论述。     

散热底板对IGBT模块功率循环老化寿命的影响

功率半导体模块通常采用减小结壳热阻的方式来降低工作结温,集成Pin-Fin基板代替平板基板是一种有效的选择。两种封装结构的热阻抗特性不同,可能对其失效机理及应用寿命产生影响。针对平板基板和集成Pin-Fin基板两种常见车规级IGBT模块进行了相同热力测试条件（结温差100 K,最高结温150℃）下的功率循环试验,结果表明,散热更强的Pin-Fin模块功率循环寿命低于平板模块。失效分析显示,两者失效模式均为键合线脱附,但Pin-Fin模块的键合失效点集中在芯片中心区域,而平板模块的键合失效点则较为分散。基于电-热-力耦合分析方法,建立功率循环试验的有限元仿真模型,结果表明,Pin-Fin模块的芯片温变梯度更大,芯片中心区域键合点温度更高,使芯片中心区域的键合点塑性变形更大,导致其寿命较平板模块更短,与试验结果吻合。     

陶瓷覆铜基板表面形貌对超声可键合性的影响

陶瓷覆铜基板在大功率电力电子器件封装模块中有着重要的应用,作为传统模块电气互连的重要组成部分,其通过超声键合技术将键合引线与其相连实现电气互连,因此,陶瓷覆铜基板的可键合性直接决定了模块生产的可靠性和成品率。以前的研究主要集中在键合参数(键合功率、键合压力、键合时间)对键合性能的影响,本文则从陶瓷覆铜基板表面形貌几何形态的角度出发,研究了其对陶瓷覆铜基板与粗铝线超声可键合性的影响。通过实验分析发现,基板表面形貌的几何特性对可键合性能有着重要的影响,一方面,表面轮廓的微观不平度的平均间距Sm(空间频率特性)影响超声可键合性。平均间距Sm越小,表面纹理越细密,其可键合区域大,键合成功率较高;反之,Sm参数太大,则会削弱基板的可键合性。另一方面,表面粗糙度Ra影响键合强度的稳定性,在键合成功的前提下,表面粗糙度越小,其键合强度的离散性越小。并利用频谱分析方法及摩擦学的理论对产生这种现象的原因进行了理论分析解释。     

金线键合线颈受损控制方法研究

本文介绍了半导体封装工艺中金线键合的基本原理,对因第一键合点线颈受损导致的产品失效进行了说明,分析了造成金线线颈受损的原因,并提出了有效的解决措施以增强金线键合的工艺控制,对半导体封装产业提供了必要的帮助和参考价值。     

导电剂对锂电池合浆工艺及性能的影响

导电剂作为锂离子电池电极配方中的重要组成部分,对降低电极和全电池电阻率,提高全电池使用性能具有重要作用,且不同类型导电剂对电池合浆工艺和电池性能具有显著影响.介绍了锂电池化学体系设计中常用的几种导电剂,分析了不同导电剂在合浆过程中的加工性能利弊,并结合导电剂的使用类型,提出了优化合浆工艺以改善电极及电池性能的方法.     

多源一体化微电源

针对无线传感网络节点和5G装置需求,开展多源一体化微电源研究,详细论述了多源集成微电源设计、单体电池制备与多源集成技术等。基于物理气相沉积技术分别研制了高效光伏电池、温差发电器件,以及薄膜储能电池,对各自的电池性能进行了优化。采用基于PCB板基的三维异构集成技术,将多源发电、微型储能及电源控制芯片一体化集成,集成一体化微电源体积3.60 cm³(包括插孔引线位),多源发电最大功率密度达到30.00 mW/cm²,系统额定输出功率密度达到1.04 mW/cm²。     

微电池的最新研究动态

电子产品小型化、微型化、集成化是当今世界技术发展的大势所趋.将微电池与微电子机械系统(MEMS)、微芯片集成在一个衬底上,制成独立的微型电子系统--系统芯片(SOC),已经不再遥远.介绍了国际上微型锌镍电池、微型固体电解质锂电池、微型太阳电池、微型温差电池及微型燃料电池和微型核电池研究工作的最新进展.     

硅片直接键合技术的研究

对硅片直接键合技术作了详细的研究；探明了合适的工艺条件，其结果键合的样品界面致密，成品率较高。     

Plasma-assisted InP-to-Si low temperature wafer bonding

The applicability of wafer bonding as a tool to integrate the dissimilar material system InP-to-Si is presented and discussed with recent examples of InP-based optoelectronic devices on Si. From there, the lowering of annealing temperature in wafer bonding by plasma-assisted bonding is the essence of this review paper. Lower annealing temperatures would further launch wafer bonding as a competitive technology and enable a wider use of it. Oxygen plasma treatment has been proven to be very feasible in achieving a strong bonding already at low temperatures. It was also seen that in our experimental setups the results depended on what plasma parameters that were used, since different plasma parameters create different surface conditions     

Wafer bonding technology and its applications in optoelectronicdevices and materials

The direct wafer bonding process has found broad applications in many critical areas including both commercial and state-of-the-art photonic devices and more recently, formation of semiconductor compliant substrates. Using the wafer bonding technology, we have demonstrated 1.3-μm vertical-cavity surface-emitting lasers (VCSELs) with a 1-mA continuous-wave (CW) threshold current and 0.83-mA pulsed threshold current. Superior device performance has also been achieved with photodetectors and micromachined tunable devices. Applying the wafer bonding process in a novel way, we have fabricated compliant universal substrates on which largely mismatched (e.g., 15% mismatch) heteroepitaxial layers can be grown defect free     

Metal‐bonding‐based hermetic wafer‐level MEMS packaging technology using in‐plane feedthrough: Hermeticity and high frequency characteristics of thick gold film feedthrough

Au–Au‐bonding‐based wafer‐level vacuum packaging technology using in‐plane feedthrough of thick Au signal lines was developed for high‐frequency micro electromechanical system (RF MEMS). Compared with conventional technology based on glass frit bonding, the developed technology is advantageous in terms of smaller width of sealing frames, lower process temperature, and smaller amount of degas. To guarantee the hermetic sealing, the adhesion between the thick Au lines and a SiOx dielectric frame is improved by an Al₂O₃ interlayer by atomic layer deposition. The steps of the dielectric frame above the thick Au lines are absorbed by an electroplated Au seal ring planarized by fly cutting. The thermocompression bonding of the Au seal rings of 20‐100 μm width was done at 300 ºC. A cavity pressure of about 500 Pa or lower was measured by “zero balance method” using Si diaphragms. Vacuum sealing was maintained for more than 19 months, and the leak rate is less than 8×10‐16 Pa m3/s. The isolation of open signal lines was measured up to 10 GHz for different designs of the sealing ring and SiOx dielectric frame. The influence of the in‐plane feed through to the isolation is as low as 2‐3 dB, if the width of the sealing ring is 20 μm and the thickness of SiOx dielectric frame is larger than 10 μm. The developed wafer‐level packaging technology is ready for applications to an radio frequency (RF) MEMS switch.     

Mechanical characterizations of topology‐insensitive rivet bonding using the sidewall bond principle

Our goal was to develop a topology‐insensitive rivet bonding method using the sidewall bond principle for MEMS devices and evaluate its mechanical characteristics. The proposed bonding method is comprised of two fundamental structures with a sidewall bond between them. The first is a male wafer having a relatively thick solder as a donor, and the second is a female wafer as an acceptor with a structure similar to a through‐via. The two wafers are bonded laterally by the reflow phenomena of the solder and the excess volume of the donor with the acceptor then generating a rivet. In this study, these structural features were investigated. The rivet bonding led to an enhancement in the bonding strength due to the plastic hardening behavior of the rivet, serving as a cushion for the stress. This was parametrically studied and experimentally verified. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Single-Crystalline Ferroelectric Thin Films by Ion Implantation and Direct Wafer Bonding

Layer splitting by helium and/or hydrogen implantation and wafer bonding was applied to transfer thin single-crystalline ferroelectric layers onto different substrates. The optimum conditions for achieving blistering/splitting after post-implantation annealing were experimentally obtained for LiNbO₃, LaAlO₃, SrTiO₃ single crystals and PLZT ceramic. Under certain implantation conditions large area exfoliation instead of blistering occurs after annealing of as-implanted substrates. Small area single-crystalline layer transfer was successfully achieved.     

1.3-μm InP-InGaAsP lasers fabricated on Si substrates by waferbonding

1.3-μm InP-InGaAsP lasers have been successfully fabricated on Si substrates by wafer bonding. InP-InGaAsP thin epitaxial films are prepared by selective etching of InP substrates and then bonded to Si wafers, after which the laser structures are fabricated on the bonded thin films. The bonding temperature has been optimized to be 400°C by considering bonding strength, quality of the bonded crystal, and compatibility with device processes. Room-temperature continuous-wave (RT CW) operation has been achieved for 6-μm-wide mesa lasers with a threshold current of 39 mA, which is identical to that of conventional lasers on InP substrates. Additionally, the lasers fabricated on Si have exhibited higher output powers than the lasers on InP, which is due to higher thermal conductivity of Si substrates. From these results, the wafer bonding is thought to be a promising technique to integrate optical devices on Si and implement optical interconnections between Si LSI chips     

A Varifocal Convex Micromirror Driven by a Bending Moment

A varifocal micromirror is designed and fabricated using silicon micromachining technology. A spherical convex surface of mirror is generated by applying a bending moment to the circumference of micromirror. This method is different from the conventional technique in which a distributed force is exerted on the central area of mirror. On the basis of the theory of materials strength, the deformation of a plate is purely spherical if only a bending moment is applied to the circumference. Spherical surface is well approximated to be a parabola if deflection is small. In order to generate only a bending moment, a force is applied to the plate in the region outside the fulcrum, by which the plate is supported freely in rotation. The proposed mirror was fabricated from a silicon on insulator wafer and a glass plate, which were connected by anodic bonding. The deviation in surface profile of mirror from a parabola was measured with an optical interferometer to be less than 4.7 nm rms in the mirror region inside the 400-mum-diameter fulcrum at the voltage lower than 215 V. The focal length of the fabricated mirror was varied from approximate infinity to 24 mm.     

纳米精度运动台电机伺服参数校准方法研究

多自由度纳米精度工件台的精度直接受电机力常数和增益平衡矩阵的影响,需要进行周期性测试。因实际电机负载与理论计算负载有差异且随时间发生改变,导致其电机力常数变化,直接采用理论计算负载会降低工件台精度。采用传递函数计算电机实际负载,建立电机负载与电机力常数间的关系,实现了电机力常数的校准。引入串扰系数描述不同电机轴间的串扰,并提出了增益平衡矩阵的详细计算方法。实验验证了该方法的正确性,并实现了工件台10 nm的定位精度。     

Hybrid integration of VCSEL's to CMOS integrated circuits

Three hybrid integration techniques for bonding vertical-cavity surface-emitting lasers (VCSELs) to CMOS integrated circuit chips have been developed and compared in order to determine the optimum method of fabricating VCSEL based smart pixels for optical interconnects and free-space optical processing. Each of the three bonding techniques used different ways of attaching the VCSEL to the integrated circuit and making electrical contacts to the n- and p-mirrors. All three techniques remove the substrate from the VCSEL wafer leaving an array of individual VCSELs bonded to individual pixels. The 4×4 and/or 8×8 arrays of bonded VCSELs produced electrical and optical characteristics typical of unbonded VCSELs. Threshold voltages down to 1.5 V and dynamic resistance as low as 30 Ω were measured, indicating good electrical contact was obtained. Optical power as high as ~10 mW for a VCSEL with a 20-μm aperture and 0.7 mW with a 6-μm aperture were observed. The VCSELs were operated at 200 Mb/s (our equipment limit) with the rise and fall times of the optical output <1 nS     

The Effect of the physico-chemical properties of cellulosic polymers on the Si wafer polishing process

Cellulosic polymers were used as organic additives to reduce the wafer surface roughness during the polishing process. The physico-chemical affinity of the polymer for the wafer and the formation of a hydro-plane on the Si wafer surface were investigated to identify the role of the polymeric additives in the wafer-polishing process. Two different polymers, hydroxyethyl cellulose (HEC) and carboxymethyl cellulose (CMC), were employed as a surface modifier for the wafer. The wettability of the Si surface varied markedly between the different suspensions prepared with HEC and CMC due to different adsorptive behaviors. As a result, the suspension prepared with HEC reduced the haze level and micro-roughness of the wafer, enhancing overall polishing performance.