一种用于数字QAM解调芯片中的盲均衡器实现

设计了一种用于数字QAM解调芯片中的自适应盲均衡器。该均衡器采用常模算法（CMA）和判决引导最小均方算法（DD-LMS）,结合判决反馈结构（DFE）,即采用前向滤波和反馈滤波两级滤波器组,该方案提高了信道的自适应性能和降低了均衡器的阶数。通过对算法的简化和电路结构的优化,减少了硬件资源,降低了电路的面积和功耗。     

一个用于高速SerDes的基于0.18um CMOS工艺的6.25Gb/s均衡器

本文介绍了一种基于0.18mm CMOS工艺,适用于高速背板传输的6.25Gb/s均衡器。该均衡器由1抽头前馈均衡器(FFE)和2抽头判决反馈均衡器(DFE)组成,能够消除前向码间干扰和后向码间干扰。FFE中的延迟线采用了有源电感峰化技术,不仅增加了带宽,也节省了面积。基于CML的加法器,触发器和选择器的使用则提高了DFE的速度。测试结果表明,对于经过衰减达22dB的30英寸信道的6.25Gb/s数据,该均衡器能够很好地进行均衡。1.8V的电源电压下的功耗为55.8mW,包括焊盘在内的整个芯片面积为0.3*0.5 mm₂。     

应用于10 Gbit/s光通信及背板传输的自适应均衡器设计

描述了一种既可用于背板传输也可用于光纤通信的高速串行收发器前端均衡器的设计。为适应光信号在传播中的色散效应,使用前馈均衡器(FFE)加判决反馈均衡器(DFE)的组合,取代了背板通信中常用的连续时间线性均衡器(CTLE)和DFE的组合。设计使用3 pre-tap、3 post-tap和1个main tap的抽头组合方式,兼顾pre-cursor和post-cursor的信号失真,有效补偿范围为15 dB。补偿系数采用完全自适应算法调整,对FFE采用模拟MSE算法调整,DFE引擎采用1/16速率数字sign-sign最小均方差(LMS)算法实现。芯片使用UMC 28 nm工艺流片,输入信号频率为10 Gbit/s。     

一种25Gbit/s CMOS判决反馈均衡器设计

为满足高速光通信系统的应用，基于标准40 nm CMOS工艺设计了一款25 Gbit/s判决反馈均衡器(DFE)电路，采用半速率结构以降低反馈路径的时序要求。主体电路由加法器、D触发器、多路复用器和缓冲器组成，为了满足25 Gbit/s高速信号的工作需求，采用电流模逻辑(CML)进行设计。经过版图设计和工艺角后仿验证，该DFE实现了在25 Gbit/s的速率下可靠工作，能提供10 dB的均衡增益，峰-峰差分输出电压摆幅约为950 mV,眼图的垂直和水平张开度均大于0.9 UI,输出抖动小于3 ps,在1.1 V的电源电压下功耗为12.5 mW,芯片版图的面积为0.633 mm×0.449 mm。     

运用误差反馈的判决反馈均衡器的性能分析

判决反馈均衡器（Decision Feedback Equalizer，DFE）能补偿具有严重符号间干扰（Inter Symbol Interference，ISI）的信道，且不存在线性均衡器增强噪声的影响。而在其基础上改进的运用误差反馈的DFE，可利用误差反馈滤波器来减少传统DFE中存在的误差信号的相关性，同时其硬件实现的复杂度没有明显提高。理论分析和仿真表明，这种方法比传统的DFE更有效，特别是针对信道有严重符号间干扰的情况。     

稀疏多径信道的T/2间隔CFE均衡器研究

完全反馈均衡器(Complete Feedback Equalizer, CFE)是判决反馈均衡器(DFE)的改进。该文提出了一种T/2分数间隔稀疏CFE(T/2 Sparse CFE, T/2-SCFE)结构,以避免接收机对于符号定时误差的敏感性,并有效利用长时延扩展多径信道的稀疏性来降低均衡器的复杂度。理论分析与基于实测信道的计算机仿真表明, T/2-SCFE均衡器对符号定时误差保持了稳健性,总体性能优于符号间隔CFE及分数间隔DFE。     

一种用于背板互连的10 Gbit/s接口电路

基于SMIC 40 nm CMOS工艺,提出了一种用于背板互连的10 Gbit/s I/O接口电路。该接口电路由前馈均衡器(FFE)、接收机前端放大器和判决反馈均衡器(DFE)组成。FFE对发射端信号进行预加重,DFE消除较大的残余码间干扰。重点分析了FFE和DFE在消除码间干扰时存在的问题。使用改进的FFE减少对发射端信号的衰减,保证信号到达接收端时具有较大幅度,实现接收机对信号的正确判决,降低系统的误码率。测试结果表明,系统数据率为10 Gbit/s,传输信道在Nyquist频率(即5 GHz)处的衰减为22.4 dB。在1.1 V电源电压下,判决器Slicer输入端信号眼图的眼高为198 mV,眼宽为83 ps。FFE的功耗为31 mW,接收机前端放大器的功耗为1.8 mW,DFE的功耗为5.4 mW。     

基于65nm工艺的双模自适应连续时间线性均衡器设计

描述了一种双模自适应连续时间线性均衡器(CTLE)的结构和电路设计。提出了一种结合HF-Boost、DC-Degeneration模式的双模CTLE,在5 Gb/s数据速率下提供最大的14 dB信道损耗补偿能力。该CTLE能够手动调节,也能进行基于二维眼图监视器算法的完全自适应调节。给出了均衡器电路的晶体管级设计和自适应算法引擎的模块级设计,并给出了仿真和测试结果。芯片采用65 nm高性能CMOS工艺制作,低剖面四边形平面封装。     

基于TAS-TIS结构和前馈路径的两级CTLE的设计

在高速接口电路中,接收机通常采用连续时间线性均衡器(Continuous-Time Linear Equalizer, CTLE)消除符号间干扰(Inter-Symbol Interference, ISI)对信号传输的影响。为提高CTLE电路的高频增益和减少芯片面积,基于UMC(United Microelectronics Corporation)28 nm工艺,设计了一款最大速率为50 Gbps的CTLE电路,其主体电路由跨导级联跨阻抗(Trans-Admittance Trans-impedance, TAS-TIS)结构和前馈路径的两级CTLE电路构成。在传统CTLE的基础上,使用有源电感做负载,以反相器为基础构建跨阻放大器和在输入管增加前馈通路等方式,有效地扩展了电路的工作频率。仿真结果显示,均衡后40 Gbps PAM4(4-Level Pulse Amplitude Modulation)信号、50 Gbps PAM4信号和28 Gbps NRZ(Non Return Zero Code)信号的眼图眼宽分别达到了0.68,0.5,0.92个码元间隔(UI),可满足后级电...     

基于非单点模糊RBF网络的判决反馈均衡器

提出了一种具有较强抗突发干扰能力的非单点模糊径向基函数（Radial Basis Function,RBF）网络判决反馈均衡器.该方法将具有前置滤波特性的非单点模糊化技术引入RBF网络,利用梯度下降法自适应调整参数.通过仿真实验,并与基于径向基函数网络的判决反馈均衡器（Radial Basis Function Network-Decision Feedback Equalizer,RBFN-DFE）和传统判决反馈均衡器（Decision Feedback Equalizer,DFE）进行比较,结果证明该方法抗突发干扰能力强,误码性能好.     

A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner

This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage.The receiver occupies 300×500/μm2.With the novel half rate period calibration clock data recovery(CDR)circuit,the receiver consumes 52 mW power.The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer(CTLE)and decision feedback equalizer(DFE).     

An Efficient VLSI Architecture for Computing Decision Feedback Equalizer Coefficients from the Channel State Information

A novel algorithm and architecture for computing the optimal decision feedback equalizer (DFE) coefficients from a channel state information (CSI) estimate is present. The proposed algorithm maps well onto a linear chain of n highly pipelineable CORDIC based processing elements. It is thus well suited for VLSI implementation. Due to the very regular data flow, the number of processing elements may be reduced without sacrificing computational latency by recycling the data through a chain of less than n processing elements.The proposed architecture computes the optimal DFE coefficients of a twelve tap symbol spaced DFE suitable for HIPERLAN I in 2.7 s and requires only 0.7 mm² area on a 0.35 m CMOS process, assuming a clock frequency of 100 MHz.     

An analog DFE for disk drives using a mixed-signal integrator

An analog adaptive decision-feedback equalizer (DFE) is described. The DFE cancels intersymbol interference using four feedback taps, and a fifth tap cancels dc offset. The coefficient for each tap is adapted using a small mixed-signal integrator. The DFE dissipates 220 mW at a data rate of 150 Mb/s. The active area is 1.8 mm² in a 1-μm CMOS process     

4 Gbit/s receiver with adaptive blind DFE

A serial backplane receiver with adaptive blind decision feedback equalisation (DFE) is proposed, which can operate at up to 4 Gbit/s over 1.2 m distance, which includes discontinuities due to the packaging and backplane connectors. A reduced complexity DFE implementation is achieved by biasing high-speed comparators. DFE coefficient calculation is not performed on every consecutive received sample, which significantly reduces the design complexity and power consumption.     

A decision-feedback equalizer with pattern-dependent feedback formagnetic recording channels

A new nonlinear equalizer for high-density magnetic recording channels is presented. It has a structure of the decision-feedback equalizer (DFE) with a nonlinear model at the feedback section and a dynamic threshold detector. The feedback nonlinear model is a sequence of look-up tables (LUTs) indexed by time, and each table is addressed by a transition pattern formed by one future and ν past transitions. We call this new nonlinear equalizer the pattern-dependent DFE (PDFE). The feedback nonlinear model cancels the trailing nonlinear intersymbol interference (ISI), and then the data decision is made by considering the precursor nonlinear ISI caused by one future symbol. We propose a tap optimization criterion SNR_d for the PDFE which in effect tries to maximize the output signal to noise ratio, and derive a closed-form solution for the tap values. We compare the detection performance of PDFE with that of the DFE and the RAM-DFE on experimental channels. The RAM-DFE is a DFE with one large LUT at its feedback section. The results show that the PDFE yields a significant performance improvement over the DFE and the RAM-DFE. Also the PDFE derived in this paper achieves a superior performance compared with the PDFE derived by the minimum mean-square-error criterion     

Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection

This paper presents an adaptive decision feedback equalizer (DFE) utilizing a hexagon eye-opening monitor to detect both the violation of the minimum eye and the severity of the violation so as to allow different step sizes to be used in search for optimal DFE tap coefficients. In addition, a new slope detection method is used to detect the deviation of received data symbols from the desired one so as to guide the direction of search for the optimal DFE tap coefficients. The proposed adaptive DFE allows designers to freely set DFE constraints such as the minimum vertical eye opening, the minimum horizontal eye opening, and the maximum jitter of the sampling clock so as to address the needs of different applications. To validate its effectiveness, the proposed adaptive DFE is embedded in a 2 Gbps serial link designed in an IBM 130 nm 1.2 V CMOS technology. The link is analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the proposed adaptive DFE is capable of opening completely closed data eyes at the far end of a 2-m FR4 channel with 75 % vertical eye opening, 78 % horizontal eye opening, and 21 % data jitter while consuming 17.38 mW.     

A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS

Along with CMOS technology scaling, ADC-based serial link receivers have drawn growing interest in backplane communications but power dissipation of the ADC and complex digital equalizer in such digital receivers can be a limiting factor in high-speed applications. Implementing analog embedded equalization within the front-end ADC structure can potentially relax the ADC resolution requirement and reduces the complexity of the DSP which results in a more energy-efficient receiver. In this paper, the equivalence between the speculative comparisons of a loop-unrolling DFE and an ADC with non-uniform quantization levels is utilized to propose a novel ADC-based DFE receiver structure. The equivalency partially compensates for the power overhead imposed by loop-unrolling DFE. The 5-bit prototype receiver with two-tap embedded DFE is designed, laid out and simulated in a 130-nm CMOS process with 1.8 Gbps data rate. With embedded DFE disabled, the receiver achieves 4.57-bits ENOB and 1.77 pJ/conv.-step FOM. With 1.8-Gbps signaling across a 48-in FR4 channel, the two-tap DFE enabled receiver opens the completely closed eye and allows for a 0.26 UI timing margin at a BER of 10⁻⁹. The total active area is 0.21 mm² and the ADC consumes 76 mW from a 1.2-V supply.     

Performance of a hybrid decision feedback equalizer structure forCAP-based DSL systems

We study the performance of a class of derision feedback equalizer (DFE) structures for high-speed digital transmission systems. We first present mathematical formulation of minimum mean-square error (MMSE) and the optimum tap coefficients for various finite-length phase-splitting equalizers over the loop in the presence of colored noise, such as near-end crosstalk (NEXT) and far-end crosstalk (FEXT). The performance of the equalizers is also analyzed in the presence of narrowband interference and the channel reflections introduced by bridged taps. The hybrid-type DFE (H-DFE) is presented as a practical equalizer structure for these applications. The results of analysis show that the H-DFE has advantages in the performance and/or in the implementation complexity as compared with the existing DFE structures. An additional advantage of the H-DFE is in the transmission systems that employ the precoding technique. The precoding for the H-DFE allows the system to track small changes in the channel     

Electrical equalization for advanced optical communication systems

We investigate equalizers for electronic dispersion compensation (EDC) of dispersion limited optical fibre communication links in combination with different modulation formats. We show that the performance of conventional equalizers including feedforward equalizer (FFE) and decision feedback equalizer (DFE) are fundamentally limited by the nonlinearity of square-law detection of the photodiode in direct detection systems. Advanced modulation formats such as differential phase shift keying (DPSK) and optical duobinary further enhance this kind of nonlinearity and degrade further FFE/DFE performance. However, nonlinear FFE–DFE and maximum likelihood sequence estimation (MLSE) take into account the mitigation of nonlinear inter symbol interference (ISI) and hence can achieve much better performance. We show that in contrast to other modulation formats, optical single sideband modulation results in approximately linear distortions after detection and thus a simple linear FFE equalizer can achieve good compensation.