基于弹性网稀疏表示的芯片参数成品率估算方法

当前集成电路芯片参数成品率估算通常预设大量扰动基函数进行芯片性能模型构建,易造成成品率估算方法复杂度过高.而若随意减少扰动基函数数量,则极易造成成品率估算精度缺失.针对此问题,本文提出一种芯片参数成品率稀疏估算方法.该方法首先根据工艺参数扰动建立具有随机不确定性的漏电功耗模型;然后按照关键度高低,利用弹性网自适应选取关键扰动基函数对漏电功耗模型进行稀疏表示建模;最后,利用贝叶斯理论及马尔科夫链方法对漏电功耗成品率进行估算.实验结果表明,该方法不仅可以使所构建的漏电功耗模型具有一般性和稀疏性优点,而且能够对漏电功耗成品率进行准确估算,与蒙特卡罗仿真结果相比估算误差不超过5%.同时,相较于蒙特卡罗采样,该方法还可以大幅减少算法仿真时间,具有更好的仿真效率.     

基于工艺参数扰动的IC参数成品率多目标优化算法

在芯片制造工艺中,参数扰动影响了集成电路（Integrated Circuit,IC）成品率,使不同参数成品率间存在着此消彼长的相互制约关系,而目前IC参数成品率优化算法却主要局限于单一优化目标问题。本文提出一种基于工艺参数扰动的参数成品率多目标优化算法。该算法针对漏电功耗成品率及芯片时延成品率,首先构建具有随机相关性的漏电功耗及芯片时延统计模型;随后根据其相互制约特性建立基于切比雪夫仿射理论的参数成品率多目标优化模型;最后利用自适应加权求和得到分布均匀的帕雷托优化解。实验结果表明,该算法对于具有不同测试单元的实验电路均可求得大约30个分布均匀的帕雷托优化解,不仅能够有效权衡多个优化目标间的相互制约关系,还可以使传统加权求和优化方法在帕雷托曲线变化率较小之处得到优化解。     

一种提高芯片良率的时序电路缓冲器插入算法

针对集成电路工艺参数波动影响芯片良率的问题,提出一种提高芯片良率的时序电路缓冲器插入算法.该算法通过蒙特卡罗仿真模拟流片后的芯片,确定时序电路中可插入缓冲器的最佳位置,在保证良率的前提下,降低了面积及成本损耗.算法经过ISCAS89的基准电路和TAU2013的电路进行仿真验证,结果表明插入缓冲器的数量小于等于触发器数量的1%,良率提高高达35.98%.     

基于容差分析的电路参数中心值设计研究

论述了电路参数设计的基本原理,提出了在PSpice 9软件上以容差分析为基础的电路参数中心值的设计方案.详细阐述了蒙特卡罗分析法、合格率的估算法及统计重心搜索法,对以蒙特卡罗分析为基础的电路合格率的统计及元件参数中心值的设计进行了研究.考虑到实际元件的容差分布对电路性能的影响,以OTL电路为例分析实现了电路性能指标满足约束条件下以合格率最大为目标的元件参数值的设计,证明了该方案的可行性.同时获得电路性能指标的统计特性及生产合格率的预测数据,对指导实际生产具有理论价值.     

HSpice在电路内部参数容差统计分析中的应用

提出一种基于HSpice的器件内部参数蒙特卡罗统计分析方法对电子电路进行仿真设计。针对PSpice软件只能采用特定库元件进行统计分析的局限性,研究HSpice蒙特卡罗分析的技巧、程序语句参数的设置、输出结果的判读等,解决基于高精度内部参数器件模型的电路性能仿真,给出应用该方法实现电路内部参数蒙特卡罗统计分析的仿真过程。可以有效地提高电路设计的准确性、可靠性和电子产品生产的合格率。实验表明这种方法可以对组成电路器件的任意参数进行蒙特卡罗统计分析,包括MOS管、运放等的模型内部参数,在优化电路设计中具有很高的实用性。     

基于全定制IP设计的漏电流功耗仿真计算方法

提出了一种自顶向下的基于晶体管级的全定制IP漏电流功耗计算方法,该方法计算快速高效,实用性强,取代了以往完全依靠软件仿真进行功耗计算的技术.在设计龙芯 号CPU中的全定制IP时应用了此方法,该芯片采用的是中芯国际0 .18μm CMOS工艺技术.为了验证该方法,把计算结果与Synopsys公司的Nanosim仿真结果进行对比,误差只有10 %左右.由于软件仿真需要大量的测试激励与计算时间,而该方法不需要外加测试激励便可以计算出全定制IP漏电流功耗,并能快速找到其模块所在位置,使设计周期大为缩短,因此完全可以针对这种计算方法开发相应软件及进行应用     

新型多功能漏电保护器芯片的设计

利用数模混合信号CMOS工艺实现了一种新型漏电开关保护器芯片.与传统的模拟电路保护芯片相比,这一芯片充分利用了数字电路带来的好处:降低了功耗,采用"定时延"方法大大提高了保护控制的精度,集成了电源的过压、过载保护功能以及自动重合闸功能,提供了适应不同应用环境的可编程性,同时对每一个输入的漏电信号都进行有效性检测,减小漏电保护器的误触发率,提高了抗干扰能力.     

基于全定制IP设计的漏电流功耗仿真计算方法

提出了一种自顶向下的基于晶体管级的全定制IP漏电流功耗计算方法,该方法计算快速高效,实用性强,取代了以往完全依靠软件仿真进行功耗计算的技术.在设计龙芯Ⅱ号CPU中的全定制IP时应用了此方法,该芯片采用的是中芯国际0.18μm CMOS工艺技术.为了验证该方法,把计算结果与Synopsys公司的Nanosim仿真结果进行对比,误差只有10%左右.由于软件仿真需要大量的测试激励与计算时间,而该方法不需要外加测试激励便可以计算出全定制IP漏电流功耗,并能快速找到其模块所在位置,使设计周期大为缩短,因此完全可以针对这种计算方法开发相应软件及进行应用.     

低功耗电流模互连电路设计

芯片长距离互连时,通过传统的插入缓冲器方法减小延迟存在功耗大、占用芯片面积多等问题。针对这些问题,提出了一种电流模互连电路。这一电路在互连线上传输的信号电压摆幅很小,从而能够有效降低互连功耗、减小信号延迟。通过综合使用强、弱两个驱动器作为信号发送器,进一步减小了信号延迟。对于10 mm的片上互连线,延迟为649 ps,功耗为498μW。为了提高电路在制造工艺发生波动时的鲁棒性,电流模互连结构在驱动电路中添加了电流偏置电路。在Hspice中进行的蒙特卡罗仿真结果表明,180 nm工艺技术下,10 mm互连线的延迟和功耗方差均值比分别为7.91%和12.7%,在工艺发生波动时电路能够稳定工作。     

一种降低电路泄漏功耗的多阈值电压方法

目前,多阈值电压方法是缓解电路泄漏功耗的有效手段之一。但是,该方法会加重负偏置温度不稳定性(NBTI)效应,导致老化效应加剧,引起时序违规。通过找到电路的潜在关键路径集合,运用协同优化算法,将关键路径集合上的门替换为低阈值电压类型,实现了一种考虑功耗约束的多阈值电压方法。基于45 nm工艺模型及ISCAS85基准电路的仿真结果表明,在一定功耗约束下,该方法的时延改善率最高可达12.97%,明显优于常规多阈值电压方法。电路的规模越大,抗泄漏功耗的效果越好。     

Parametric yield prediction of complex, mixed-signal IC's

A method is presented which helps the designer predict the parametric yield of complex mixed-signal IC's in a reasonable time. It builds on previous approaches to IC yield prediction employing a Monte Carlo approach for flexibility, with behavioral simulation and response surfaces for speed. To analyze complex mixed-signal IC's, a novel feature termed the correction layer is introduced. Complex mixed-signal IC's have tests which are highly nonlinear. Consequently, it can be difficult to build accurate response surfaces whose response variables are the results of such tests. The correction layer is introduced to overcome this problem. It enables a response surface to be accurately used by the method. A commercial hard disk drive IC is analyzed as an example to show the necessity of having the correction layer in order to produce accurate parametric yield predictions     

DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability

In the deep-submicrometer design regime, RF circuits are expected to be increasingly susceptible to process variations, and thereby suffer from significant loss of parametric yield. To address this problem, a postmanufacture self-tuning technique that aims to compensate for multiparameter variations is presented. The proposed method incorporates a “response feature” detector and “hardware tuning knobs,” designed into the RF circuit. The RF device test response to a specially crafted diagnostic test stimulus is logged via the built-in detector and embedded analog-to-digital converter. Analysis and prediction of the optimal tuning knob control values for performance compensation is performed using software running on the baseband DSP processor. As a result, the RF circuit performance can be diagnosed and tuned with minimal assistance from external test equipment. Multiple RF performance parameters can be adjusted simultaneously under tuning knob control. The proposed concepts are illustrated for an RF low-noise amplifier (LNA) design and can be applied to other RF circuits as well. A simulation case study and hardware measurements on a fabricated 1.9-GHz LNAs show significant parametric yield enhancement (up to 58%) across the critical RF performance specifications of interest.      

Novel Semi-Analytical Method for BER Evaluation in Simulated Optical DQPSK Systems

A novel semi-analytical method for optical differential quadrature phase-shift keying systems performance evaluation based on the equivalent differential phase (EDP) is proposed. The proposed method is computationally much faster than Monte-Carlo (MC) simulation and methods based on the combination of MC simulation with the EDP. Discrepancies not exceeding 0.2 dB on the required optical signal-to-noise ratio are obtained between MC simulation and the proposed method.      

Performance analysis of MC‐CDMA by employing the MMSE‐PIC scheme in wireless communications

From the past decade, the multicarrier code division multiple access (MC‐CDMA) transmission schemes have placed major role in wireless communications. It is providing a secured wireless communication to the users with guaranteed performance. In many situations, the performance of the MC‐CDMA is restricted due to the interference caused by multiple access interference (MAI), which also influences the frameworks of CDMA. To overcome this issue, we concentrated on developing the efficient technique for data transmission with interference cancellation for downlink MC‐CDMA. In the proposed method, the interference cancellation procedure is done by using the regeneration and subtraction of MAI from the signal. The simulation results are evaluated using the MC‐CDMA system with different decision functions. Results proved that the proposed system is efficient in reducing the MAI along with an improved bit error rate (BER).     

Genetic algorithm-based partial charging schedule of rechargeable sensor networks

The use of rechargeable sensors is a promising solution for wireless sensor networks. On this type of network, mobile charging vehicles (MC) are used for charging sensors using wireless energy transfer (WET) technology. In on-demand charging, a sensor transmits a charging request to the service station, and the MC visits the sensor to transfer energy. The key disadvantages of utilizing MC-based WET are its high energy expenditure rate due to mobility, long service time, and slow charging rate. Because of these reasons, sensors deplete their energy and become dead before the MC reaches the requesting nodes to recharge. We have adapted a genetic algorithm-based partial charging scheme to serve the charging requests. Our objective is to improve the survival ratio of the network. Using comprehensive simulations, we analyze the performance of our proposed method and compare it to two other existing approaches. The simulation results demonstrate that our proposed algorithm improves the survival ratio by up to 20 % by developing a dynamic energy threshold function for transmitting charging requests from the sensors and a partial charging schedule using a genetic algorithm.     

Adaptive Compensation Method Using the Prediction Algorithm for the Doppler Frequency Shift in the LEO Mobile Satellite Communication System

In low earth orbit (LEO) satellite communication systems, more severe phase distortion due to Doppler shift is frequently detected in the received signal than in cases of geostationary earth orbit (GEO) satellite systems or terrestrial mobile systems. Therefore, an estimation of Doppler shift would be one of the most important factors to enhance performance of LEO satellite communication system. In this paper, a new adaptive Doppler compensation scheme using location information of a user terminal and satellite, as well as a weighting factor for the reduction of prediction error is proposed. The prediction performance of the proposed scheme is simulated in terms of the prediction accuracy and the cumulative density function of the prediction error, with considering the offset variation range of the initial input parameters in LEO satellite system. The simulation results showed that the proposed adaptive compensation algorithm has the better performance accuracy than Ali's method. From the simulation results, it is concluded the adaptive compensation algorithm is the most applicable method that can be applied to LEO satellite systems of a range of altitude between 1,000 km and 2,000 km for the general error tolerance level, M = 250 Hz.     

Parametric manufacturing yield modeling of GaAs/AlGaAs multiplequantum well avalanche photodiodes

GaAs/AlGaAs multiple quantum well (MQW) avalanche photodiodes (APD's) are of interest as an ultra-low noise image capture mechanism for high-definition systems. Since literally millions of these devices must be fabricated for imaging arrays, it is critical to evaluate potential performance variations of individual devices in light of the realities of semiconductor manufacturing. Specifically, even in a defect-free manufacturing environment, random variations in the fabrication process will lead to varying levels of device performance, Accurate device performance prediction requires precise characterization of these variations. This paper presents a systematic methodology for modeling the parametric performance of GaAs MQW APD's. The approach described requires a model of the probability distribution of each of the relevant process variables, as well as a second model to account for the correlation between this measured process data and device performance metrics. The availability of these models enables the computation of the joint probability density function required for predicting performance using the Jacobian transformation method. The resulting density function can then be numerically integrated to determine parametric yield. Since they have demonstrated the capability of highly accurate function approximation and mapping of complex, nonlinear data sets, neural networks are proposed as the preferred tool for generating the models described above. In applying this methodology to MQW APD's, it is shown that using a small number of test devices with varying active diameters, barrier and well widths, and doping concentrations enables prediction of the expected performance variation of APD gain and noise in larger populations of devices. This approach compares favorably with Monte Carlo techniques and allows device yield prediction prior to high volume manufacturing in order to evaluate the impact of both design decisions and process capability     

Parametric SNR Estimation Based on Auto-Regressive Model in AWGN Channels

Signal-to-noise ratio（SNR）estimation for signal which can be modeled by Auto-regressive（AR）process is studied in this paper.First,the conventional frequency domain method is introduced to estimate the SNR for the received signal in additive white Gauss noise（AWGN）channel.Then a parametric SNR estimation algorithm is proposed by taking advantage of the AR model information of the received signal.The simulation results show that the proposed parametric method has better performance than the conventional frequency doma in method in case of AWGN channel.     

Cluster-based delta-QMC technique for fast yield analysis

Monte Carlo (MC) analysis is often considered a golden reference for yield analysis because of its high accuracy. However, repeating the simulation hundreds of times is often too expensive for large circuit designs. The most widely used approach to reduce MC complexity is using efficient sampling methods to reduce the number of simulations. Aside from those sampling techniques, this paper proposes a novel approach to further improve MC simulation speed with almost the same accuracy. By using an improved delta circuit model, simulation speed can be improved automatically due to the dynamic step control in transient analysis. In order to further improve the efficiency while combining the delta circuit model and the sampling technique, a cluster-based delta-QMC technique is proposed in this paper to reduce the delta change in each sample. Experimental results indicate that the proposed approach can increase speed by two orders of magnitude with almost the same accuracy, which significantly improves the efficiency of yield analysis.