VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters

In this paper, a VLSI architecture for lifting-based shape-adaptive discrete wavelet transform (SA-DWT) with odd-symmetric filters is proposed. The proposed architecture is comprised of a stage-based boundary extension strategy and the shape-adaptive boundary handling units. The former could reduce the complexity of multiplexers that are introduced to solve the shape-adaptive boundary extension. The latter consists of two multiplexers and can solve the shape-adaptive boundary extension locally without any additional register. Two case studies are presented, including the JPEG 2000 default (9, 7) filter and MPEG-4 default (9, 3) filter. According to comparison results with previous architectures, the efficiency of the proposed architectures is proven.Chao-Tsung Huang was born in Kaohsiung, Taiwan in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan in 2001. He is currently working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for 1-D, 2-D, and 3-D Discrete Wavelet Transform. cthuang@video.ee.ntu.edu.twPo-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems. pctseng@video.ee.ntu.edu.twLiang-Gee Chen (S84–M86–SM94–F01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi. lgchen@video.ee.ntu.edu.tw     

一种适合JPEG2000的离散小波变换VLSI统一结构

提出了一种基于提升算法(1ifting)的离散小波变换(DWT)统一结构。它无需额外的边界延拓过程，经配置后可适用于JPEG2000中的无损或有损小波变换。通过将边界延拓过程内嵌于离散小波变换中，可以降低功耗，减少所需内存。为了达到更高的处理速度和硬件利用率，采用了流水线和折叠结构。这种高效紧凑的离散小波变换结构适用于JPEG2000编码器和各种实时图像／视频应用系统．     

一维离散小波变换VLSI结构分析设计

提升算法的推出使得离散小波变换硬件的快速实现成为可能。翻转结构在提升架构的基础上进一步提高运算速度。在此,对翻转结构的舍入误差进行了分析,在翻转结构的基础上,对提升步骤进行了合并,提出一种有效的DWT硬件实现方案。实验结果表明,通过采用流水线模式提出的这种硬件结构,在关键路径约束的条件下,可以充分利用硬件资源。     

二维DWT／IDWT处理器的VLSI设计

在本文中，我们设计了基于多分辨分析，适合于硬件实现的二维ＤＷＴ和ＩＤＷＴ实时系统，采用了ｔｏｐ－ｄｏｗｎ的ＶＬＳＩ设计方法，用硬件描述语言ＶＨＤＬ，在Ｓｙｎｏｐｓｙｓ系统中进行了验证和综合，综合结果表明：系统的规模为７１４０单元面积，对于四层信小波变换，数据处理速度约可达到４Ｍｐｉｘｅｌ／ｓ。     

离散小波变换的VLSI实现

离散小波变换已广泛应用于信号处理中。然而,实时小波变换需要大量运算,因此,专用小波变换芯片的设计已成为信号处理中的关键技术。文章提出了一种小波变换递归金字塔算法的VLSI结构,采用一组输入延迟单元和一个控制单元,用一组并行滤波器完成了小波变换。编写了相应的Verilog HDL模块,并进行了仿真和逻辑综合。     

A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform

Many VLSI architectures for computing the discrete wavelet transform (DWT) were presented, but the parallel input data sequence and the programmability of the 2-D DWT were rarely mentioned. In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transform levels. The proposed architecture is very regular and easy for extension. To eliminate high frequency components, the pixel values outside the boundary of the image are mirror-extended as the symmetric wavelet transform (SWT) and the mirror-extension is realized via the routing network. Owing to the property of the parallel processing, we adopt the row-based recursive pyramid algorithm (RPA), similar to 1-D RPA, as the data scheduling. This design has been implemented and fabricated in a 0.35 m 1P4M CMOS technology and the working frequency is 50 MHz. The chip size is about 5200 m × 2500 m. For a 256 × 256 image, the chip can perform 30 frames per second with the filter length varying from 2 to 20 and with various levels. The proposed architecture is suitable for real-time applications such as JPEG 2000.     

一种新型基于提升算法的二维离散小波变换结构的实现

在提升算法原理分析的基础上，设计出一种采用提升算法的二维离散小波变换结构，改变了传统的提升算法先行后列的运算方式，将行列运算操作结合起来进行，这样，相比于传统结构，在基本不增加硬件单元的前提下，变换时间减小为原来的75％左右，提高了硬件效率。     

一种基于提升的二维离散小波变换VLSI架构

离散小波变换(Discrete Wavelet Transform,DWT)需要较多的运算量以及较大的存储器空间,为了使之适用于实时的图像处理应用,就需要开发特殊的架构和芯片来提高离散小波变换的运算性能。基于提升的二维DWT提出了一种新型的VLSI结构——LLSP架构,其结合逐级和基于行的架构这两者特点,带来了硬件开销和存储器空间的降低,并可以用于多提升步骤的扩展以及多级二维离散小波变换。     

二维正交子波变换的VLSI并行计算

本文提出一个二维离散正交子波变换的ＶＬＳＩ并行结构，该结构将二维输入信号分解成不重叠的若干行组，从而使每组中的所有行被并行处理，而不同组的行的处理、不同级上的计算，以至不同信号的计算可以在此结构上流水线地进行。     

逆向工程中对离散点云的特征识别算法探究

基于逆向设计中点云处理的表面识别问题,本文提出了一种基于小波变换的离散点云数据的特征识别算法。首先将离散点云表示成小波变换可以处理计算的形式,然后在此基础上提出了具体的二维和三维离散点云的小波分解算法,最后引入实例,对二维离散点云的小波分解算法进行验证分析。实验结果表明本文提出的算法达到了对点云数据的特征分解的目的。将离散点云数据按特征分解从而提取出不同的特征成分,可以根据后期点云预处理的不同要求,将小波变换后的数据进行进一步的处理。     

逆向工程中对离散点云的特征识别算法探究

基于逆向设计中点云处理的表面识别问题,本文提出了一种基于小波变换的离散点云数据的特征识别算法。首先将离散点云表示成小波变换可以处理计算的形式,然后在此基础上提出了具体的二维和三维离散点云的小波分解算法,最后引入实例,对二维离散点云的小波分解算法进行验证分析。实验结果表明本文提出的算法达到了对点云数据的特征分解的目的。将离散点云数据按特征分解从而提取出不同的特征成分,可以根据后期点云预处理的不同要求,将小波变换后的数据进行进一步的处理。     

二维离散小波变换的VLSI实现

小波变换图像编码获得了比传统DCT变换编码更好的图像质量和更高的压缩比,然而,实时二维小波变换需要大量运算,因此,专用小波变换芯片的设计已成为小波图像编码中的关键技术,文章提出了一种高速的二维小波变换的VLSI结构。根据模块化的设计思想,设计出一组二维小波变换的基本模块。通过将这些模块按变换要求适当组装,完成了多级二维小波变换,编写了相应的VerilogHDL模型,并进行了仿真和逻辑综合。     

二维离散小波变换的FPGA实现

依据传统的Mallat算法,提出了一种基于FPGA实现的高速二维小波变换的方法.该方法采用模块化设计,通过将这些模块按变换要求适当级联,可轻松实现多级二维离散小波分解.用Verilog HDL实现了相关模块,并进行了仿真和逻辑综合.     

An Efficient VLSI Architecture for the Computation of 1-D Discrete Wavelet Transform

This paper presents a new architecture for VLSI implementation of the one dimensional Discrete Wavelet Transform (DWT). The architecture uses single filter for generation of both the DWT coefficients and scaling function for orthogonal wavelets as opposed to the conventional two filter approach. For multilevel decomposition, the fold back architecture principle, which interleaves the decimated scaling function back into the filter for subsequent levels, is applied. Limited use of memory in the design enables efficient implementation of the DWT computation in VLSI.     

Low-power Analog VLSI Implementation of Wavelet Transform

For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.     

基于离散平稳小波变换的红外图像对比度增强

提出一种基于离散平稳小波变换的红外图像增强方法,对红外图像进行离散平稳小波 变换后,分别对各个分解层的高频子带利用所提出的非线性增强方法进行对比度增强。实验结果表明,本文提出的方法在有效的提高红外图像中目标对比度的同时,又能突出红外图像的细节部分信息。算法在性能上优于传统的直方图均衡法、反锐化掩膜法和基于离散正交小波变换的对比度增强方法。     

连续小波变换VLSI实现综述

小波变换是信号处理、图像压缩和模式识别等诸多领域中一个非常有效的数学分析工具。然而，实时小波变换计算量大，需要专用硬件来实现。连续小波变换的VLSI实现在处理速度、功耗及适用频率范围方面部具有较明显的优势，且实现方法灵活。本文对近年来有关该领域的研究情况作了综合评述，讨论了其中存在的问题，并指出了今后的若干发展方向，特别是瞬时缩展电路技术是实现低电压低功耗小波变换芯片的重要途经之一。     

基于离散插值样条的提升小波变换

文中引入了一种对信号递归滤波的提升方法,该方法与通常的提升方法不同之处是使用IIR滤波器.探讨了空间域中基于离散插值样条的预测算子和更新算子的设计.提出的方法以插值为基础,只涉及信号的采样,不要求使用正交公式,更适合信号的处理.最后由数值仿真验证了该算法的性能,对于软阈值法小波系数去噪,提升小波变换T12同B9/7相比,前者略优于后者,提升方法的优点在于其设计上的灵活性和计算花费少.     

一维离散小波变换的VLSI设计

文章提出了一种离散小波变换的VLSI结构。这种结构由四部分构成：输入延迟单元、寄存器单元、滤波器单元和控制单元。该结构采用了递归金字塔算法(RPA)取代传统的PA算法。只用一组滤波器即可完成所有级别的小波运算。同时，结合Short-Length FIR技术，以减少乘法和加法的运算次数。在寄存器单元的设计上，采用了Lifetime Analysis技术，结合Forward-Backward Register Allocation(FBRA)方法，使寄存器的数目降至最低。     

JPEG2000的53小波提升方法的DSP的并行实现

提出了两种不同的，基于DSP芯片TMS320VC5502的，具有并行运算特点的5／3小波提升方法的硬件实现方案；并且分析了两种方案的效率差异。实验证实，两种方案均明显缩短了对图像数据进行离散小波变换的时间。