A synthesis methodology for ECL circuits based on mixed voltage-current representation

This paper presents a synthesis methodology for ECL circuits based on a mixed voltage-current signal representation and operation defined on the voltage and current signals. The ideas presented in this paper are then demonstrated on the design of an BCL 1-bit full adder. The paper concludes by presenting an algebraic system which is suitable for current signal representation and operation on currents.     

Partitioning-based algorithm for synthesis of low-powercombinational circuits

The authors propose a synthesis algorithm for the low-power design of combinational circuits. Experimental results show the effectiveness of the proposed algorithm by generating a restructured circuit with low power consumption     

A general method in synthesis of pass-transistor circuits

A general method in synthesis and signal arrangement in different pass-transistor network topologies is analyzed. Several pass-transistor logic families have been introduced recently, but no systematic synthesis method is available that takes into account the impact of signal arrangement on circuit performance. In this paper we develop a Karnaugh map based method that can be used to efficiently synthesize pass-transistor logic circuits, which have balanced loads on true and complementary input signals. The method is applied to the generation of basic two-input and three-input logic gates in CPL, DPL and DVL. The method is general and can be extended to synthesize any pass-transistor network.     

Techniques for the optimal design and synthesis of switching circuits

The variational approach to the optimal design of high-speed switching circuits is explored. The approach implements the variational calculus to obtain an expression for the vector sensitivity of a scalar performance function (e.g., delay, or switching time) to changes in the vector of design parameters. Gradient methods are established for using the vector sensitivity to iteratively update the parameter vector and obtain an optimal design. It is shown that the variational approach retains, typically, an M-fold computational advantage over conventional step-and-repeat methods in determining the sensitivity of a scalar performance function to M design parameters. The approach is shown to be well adapted for incorporation into package analysis programs with matrix formulations, and vested with sufficient generality to be applicable to a wide range of switching circuit problems (e.g., low-power or large-scale integrated circuits). It is further shown that subsumed in the general class of nonlinear parameter-value synthesis problems is the class of delay-minimization problems, and that the switching time minimization problem is a special case of the classical "time-optimal" problem.     

Phase assignment for synthesis of low-power domino circuits

High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs but domino logic comes at a heavy cost in terms of total power dissipation. A set of results related to automated phase assignment for the synthesis of low-power domino circuits is presented: (1) it is demonstrated that the choice of phase assignment at the primary outputs of a circuit can significantly impact lower dissipation in the domino block, and (2) a method to determine a phase assignment that minimises power consumption in the final circuit implementation is proposed. Preliminary experimental results on a mixture of public domain benchmarks and real industry circuits show potential power savings as high as 34% over the minimum area realisation of the logic. Furthermore, the low-power synthesised circuits still meet timing constraints     

`Transition equations? for the analysis and synthesis of sequential circuits

Transition equations are introduced as an alternative to existing methods of analysing and synthetising clocked sequential switching circuits. The method has the particular merits of allowing for the representation and manipulation of propagation delays and of providing an easy means of dealing with cascaded edge triggered bistable arrays. Examples are given.     

Automation of the synthesis of asynchronous sequential circuits

The automation of a method for synthetising asynchronous sequential circuits is reported. The method is suitable for circuits having transition and level inputs. Inclusion relations between state-pair sets and partitions are used for the selection of suitable partitions for an economic race-free state assignment of minimum transition time.     

Design and synthesis of dynamic circuits

Dynamic circuits are widely used in today's high-performance microprocessors for obtaining timing goals that are not possible using static CMOS circuits. Currently, no commercial tools are able to synthesize dynamic circuits and therefore their design is either completely done by hand or aided by proprietary in-house design tools. This paper describes methodologies and tools for the design and synthesis of dynamic circuits, including general monotonic circuits, which consist of alternating low-skew and high-skew logic gates that may both contain functionality. Synthesis results show standard domino, dynamic-static domino, monotonic static CMOS, zipper CMOS, and footless domino and clock-delayed domino circuits to have average speed improvements of 1.57, 1.66, 1.67, 1.47, 1.71, and 1.60 times over static CMOS, respectively.     

绝热无比型动态触发器和同步时序电路综合

该文从电路三要素理论出发研究低功耗电路，定量描述绝热无比型动态记忆电路。绝热无比型动态触发器利用电容接收和保存信息，避免目前绝热电路中电容上的信息得而复失的现象，其中绝热D和T'触发器只用6管，带‘与或非’输入的绝热D触发器只用9管。在上述理论基础上该文提出绝热无比型动态同步时序电路综合方法，用此法设计出绝热5421BCD码十进制计数器，仅用32管，总功耗小于一个PAL－2N四位二进制计数器的功耗，计算机模拟验证该文方法正确。     

Logic synthesis of race-free asynchronous CMOS circuits

A synthesis method for generating race-free asynchronous CMOS circuits that are independent of the internal and output delays is presented. The design method is based on the properties of the negative gates. An inertial delay is associated with each negative gate in a CMOS circuit. Such a gate model is quite realistic. The basic principle of the method presented is to augment and to modify the original flow table in such a way that the obtained logic diagram contains only negative gates. In addition, the synthesis method is capable of avoiding any race, and consequently any critical race or hazard. The method minimizes the number of internal variables and therefore the number of gates, providing new simple cells for fast and low-power integrated circuits     

Systematic synthesis of combinational circuits using multiplexers

An algorithmic procedure has been developed, suited to computer solution, for a switching function of n variables that can be synthesised by one multiplexer MUX(p, q), (n?q > l) without the necessity of referring to all the possible Ashenhurst's decomposition charts DCn(?q|?n?q).     

Automated topology synthesis of analog and RF integrated circuits: A survey

The puzzle of automatically synthesizing analog and radio frequency (RF) circuit topology has not yet been offered with an industrially-acceptable solution although endeavors still continue to seek a conquest in this area. This survey provides a comprehensive study of the techniques utilized for this purpose. The existing methods are analyzed from four different viewpoints, namely, structural view, conceptual view, implementation view, and application view. Different schemes are perused with their advantages and drawbacks discussed in the context of balanced performance between configuration-space coverage and search efficiency. Some prospective trends are pointed out to shed light on the upcoming research activities.     

Wakeup scheduling and its buffered tree synthesis for power gating circuits

Power gating circuit suffers from large amount of rush current during wakeup, especially when all switch cells are turned on simultaneously. If each switch cell is turned on at a different time, rush current can be reduced. It is shown in this paper that rush current can be reduced even more if signal transition time (or signal slew) to each switch cell is adjusted. We define wakeup scheduling as to determine turn-on time and signal slew of each switch cell; the goal is to minimize wakeup delay while keeping rush current below the maximum value that is allowed. The determined turn-on time and signal slew are implemented using a buffered tree. The wakeup scheduling and buffered tree construction are integrated into a design flow. To adapt to process variation, we use adjustable delay buffers in the wakeup network. We also apply grid-based design flow and use Schmitt triggers to implement large designs. Experiments in an industrial 1.1 V, 32-nm technology demonstrate that the wakeup delay is reduced by 12% on average of example circuits compared with turn-on scheduling.     

A high-slew integrator for switched-capacitor circuits

A new method for improving the slew rate of a switched-capacitor integrator is introduced. A booster circuit is used to measure the integrator input voltage and then inject a proportionate amount of charge at the integrator output. The boosted integrator significantly reduces the settling time due to amplifier slewing. In addition, the booster has no adverse effect on the noise and stability performance of the integrator. The booster stage increases the total static integrator power by 36% and the total die area by 22%     

A direct translation reading aid for the blind

A reading device for the blind is proposed in which a facsimile of ordinary printed material is presented tactually. The tactile image is presented by a dense array of pins which can be made to vibrate individually through perforations in a plate on which the user's finger is rested. In the arrangement proposed, the image of ordinary printed matter is focused on an array of photocells which are coupled one-to-one to piezoelectric reeds which drive the image-producing pins. The feasibility of this arrangement has been evaluated, and relations among the design parameters are derived. The power required to drive each pin for adequate tactile stimulation is shown to be only about 30 µW. Present photocell sensitivities and integrated circuit techniques appear to be adequate for a convenient microminiature realization of this arrangement, although several technical development problems remain to be solved. Successful reading tests with blind subjects are reported in which a computer controller simulates the optical portion of the system. The tactile images presented on a field of 96 piezoelectrically driven pins have been readable by the three subjects tested at rates of about 30 correct words per minute.     

New experiments on iterative synthesis of combinational circuits

A new strategy is presented for experiments on iterative synthesis of combinational circuits within a gate-array or an FPGA library. Results thus obtained are presented. Reductions in circuit complexity are achieved with each of the libraries.