Partitioning-based algorithm for synthesis of low-powercombinational circuits

The authors propose a synthesis algorithm for the low-power design of combinational circuits. Experimental results show the effectiveness of the proposed algorithm by generating a restructured circuit with low power consumption     

A general method in synthesis of pass-transistor circuits

A general method in synthesis and signal arrangement in different pass-transistor network topologies is analyzed. Several pass-transistor logic families have been introduced recently, but no systematic synthesis method is available that takes into account the impact of signal arrangement on circuit performance. In this paper we develop a Karnaugh map based method that can be used to efficiently synthesize pass-transistor logic circuits, which have balanced loads on true and complementary input signals. The method is applied to the generation of basic two-input and three-input logic gates in CPL, DPL and DVL. The method is general and can be extended to synthesize any pass-transistor network.     

Techniques for the optimal design and synthesis of switching circuits

The variational approach to the optimal design of high-speed switching circuits is explored. The approach implements the variational calculus to obtain an expression for the vector sensitivity of a scalar performance function (e.g., delay, or switching time) to changes in the vector of design parameters. Gradient methods are established for using the vector sensitivity to iteratively update the parameter vector and obtain an optimal design. It is shown that the variational approach retains, typically, an M-fold computational advantage over conventional step-and-repeat methods in determining the sensitivity of a scalar performance function to M design parameters. The approach is shown to be well adapted for incorporation into package analysis programs with matrix formulations, and vested with sufficient generality to be applicable to a wide range of switching circuit problems (e.g., low-power or large-scale integrated circuits). It is further shown that subsumed in the general class of nonlinear parameter-value synthesis problems is the class of delay-minimization problems, and that the switching time minimization problem is a special case of the classical "time-optimal" problem.     

Phase assignment for synthesis of low-power domino circuits

High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs but domino logic comes at a heavy cost in terms of total power dissipation. A set of results related to automated phase assignment for the synthesis of low-power domino circuits is presented: (1) it is demonstrated that the choice of phase assignment at the primary outputs of a circuit can significantly impact lower dissipation in the domino block, and (2) a method to determine a phase assignment that minimises power consumption in the final circuit implementation is proposed. Preliminary experimental results on a mixture of public domain benchmarks and real industry circuits show potential power savings as high as 34% over the minimum area realisation of the logic. Furthermore, the low-power synthesised circuits still meet timing constraints     

`Transition equations? for the analysis and synthesis of sequential circuits

Transition equations are introduced as an alternative to existing methods of analysing and synthetising clocked sequential switching circuits. The method has the particular merits of allowing for the representation and manipulation of propagation delays and of providing an easy means of dealing with cascaded edge triggered bistable arrays. Examples are given.     

Automation of the synthesis of asynchronous sequential circuits

The automation of a method for synthetising asynchronous sequential circuits is reported. The method is suitable for circuits having transition and level inputs. Inclusion relations between state-pair sets and partitions are used for the selection of suitable partitions for an economic race-free state assignment of minimum transition time.     

A high-slew integrator for switched-capacitor circuits

A new method for improving the slew rate of a switched-capacitor integrator is introduced. A booster circuit is used to measure the integrator input voltage and then inject a proportionate amount of charge at the integrator output. The boosted integrator significantly reduces the settling time due to amplifier slewing. In addition, the booster has no adverse effect on the noise and stability performance of the integrator. The booster stage increases the total static integrator power by 36% and the total die area by 22%     

Logic synthesis of race-free asynchronous CMOS circuits

A synthesis method for generating race-free asynchronous CMOS circuits that are independent of the internal and output delays is presented. The design method is based on the properties of the negative gates. An inertial delay is associated with each negative gate in a CMOS circuit. Such a gate model is quite realistic. The basic principle of the method presented is to augment and to modify the original flow table in such a way that the obtained logic diagram contains only negative gates. In addition, the synthesis method is capable of avoiding any race, and consequently any critical race or hazard. The method minimizes the number of internal variables and therefore the number of gates, providing new simple cells for fast and low-power integrated circuits     

Systematic synthesis of combinational circuits using multiplexers

An algorithmic procedure has been developed, suited to computer solution, for a switching function of n variables that can be synthesised by one multiplexer MUX(p, q), (n?q > l) without the necessity of referring to all the possible Ashenhurst's decomposition charts DCn(?q|?n?q).     

A direct translation reading aid for the blind

A reading device for the blind is proposed in which a facsimile of ordinary printed material is presented tactually. The tactile image is presented by a dense array of pins which can be made to vibrate individually through perforations in a plate on which the user's finger is rested. In the arrangement proposed, the image of ordinary printed matter is focused on an array of photocells which are coupled one-to-one to piezoelectric reeds which drive the image-producing pins. The feasibility of this arrangement has been evaluated, and relations among the design parameters are derived. The power required to drive each pin for adequate tactile stimulation is shown to be only about 30 µW. Present photocell sensitivities and integrated circuit techniques appear to be adequate for a convenient microminiature realization of this arrangement, although several technical development problems remain to be solved. Successful reading tests with blind subjects are reported in which a computer controller simulates the optical portion of the system. The tactile images presented on a field of 96 piezoelectrically driven pins have been readable by the three subjects tested at rates of about 30 correct words per minute.     

A one-pin crystal oscillator for VLSI circuits

The oscillator features the same stability, reliability, and ease of use as the common Pierce oscillator; however, only one package pin and no external components other than the crystal need be dedicated to the oscillator. The design is quite general, and may be implemented in either NMOS or CMOS technologies, using only a moderate amount of silicon area. Design examples are given, and the fabrication results are presented.     

A sinusoidal voltage-controlled oscillator for integrated circuits

This article describes an inductorless near-harmonic voltage-controlled oscillator circuit that utilizes a compensated Wien-bridge topology with a voltage-controlled Miller integrator as the tuning element. Suitable for monolithic integrated realization, the VCO offers a two-to-one control range for frequencies up to 10 MHz, with less than a 1-dB amplitude variation and less than a ten percent total harmonic distortion over the entire control range.     

New experiments on iterative synthesis of combinational circuits

A new strategy is presented for experiments on iterative synthesis of combinational circuits within a gate-array or an FPGA library. Results thus obtained are presented. Reductions in circuit complexity are achieved with each of the libraries.     

A test generation program for sequential circuits

This article presents an automatic test pattern generation system based on both algebraic and topological techniques. Circuit partitioning, testability measures, 9-valued functions, pruning heuristics, and interactive fault simulation are employed to increase the performance of a modified version of the sequential D-Algorithm. Test generation results for someIscas'89 circuits are presented.Enrico Macii is also with Politecnico di Torino, Dip. di Automatica e Informatica, Torino, Italy 10129.     

A new DFT methodology for sequential circuits

This paper introduce a new design for testability methodology for sequential circuits based on input/output pin utilization which exploits the possibility of applying test patterns in parallel. The goal is to reduce the test application time maintaining the same fault coverage as the one obtained using full scan. The proposed procedure includes necessary and sufficient conditions which are easily incorporated in a design system and produce the required implementation. Successful experimental results are presented on benchmark circuits:IC test length is reduced on an average by 44% of full scan.This work is partly supported by research grants from the Natural Sciences and Engineering Research Council of Canada and equipment grants from the Canadian Microelectronics Corporation.