CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively     

A new Al0.3Ga0.7As/GaAs modulation-doped FET

A new Al0.3Ga0.7As/GaAs modulation-doped FET fabricated like a MESFET but operating like a JFET was successfully fabricated and tested. This new device replaces the Schottky gate of the MESFET with an n+/p+ camel diode structure, thereby allowing problems associated with the former to be overcome. The devices, which were fabricated from structures grown by molecular beam epitaxy (MBE), had a 1µm gate length, a 290µm gate width, and a 4µm channel length. The room temperature transconductance normalized to the gate width was about 95 mS/mm, which is comparable to that obtained in similar modulation-doped Schottky barrier FET's. Unlike modulation-doped Schottky barrier FET's, fabrication of this new device does not require any critical etching steps or formation of a rectifying metal contact to the rapidly oxidizing Al0.3Ga0.7As. Relatively simple fabrication procedures combined with good device performance make this camel gate FET suitable for LSI applications.     

One transistor ferroelectric memory with Pt/Pb5Ge3O11/Ir/poly-Si/SiO2/Si gate-stack

One transistor ferroelectric nonvolatile memory with gate stack of Pt/Pb₅Ge₃O₁₁/lr/poly-Si/SiO₂ /Si was successfully fabricated. This device features a saturated memory window of 3 V at a programming voltage of higher than 3 V from C-V and I-V measurements. The memory window decays rapidly within 10 seconds after programming, but remains stable at 1 V for up to 100 h. The "on" and "off" state currents are greater than 10 μA/μm and less 0.01 pA/μm, respectively, at a drain voltage of 0.1 V     

High-linearity high-current-drivabilityGa0.51In0.49P/GaAs MISFET usingGa0.51In0.49P airbridge gate structure grown byGSMBE

A novel structure Ga_0.51In_0.49P/GaAs MISFET with an undoped Ga_0.51In_0.49P layer serving as the airbridge between active region and gate pad was first designed and fabricated. Wide and flat characteristics of g_m and f_max versus drain current or gate voltage were achieved. The device also showed a very high maximum current density (610 mA/mm) and a very high gate-to-drain breakdown voltage (25 V). Parasitic capacitances and leakage currents were minimized by the airbridge gate structure and thus high f_T of 22 GHz and high f_max of 40 GHz for 1 μm gate length devices were attained. To our knowledge, both were the best reported values for 1 μm gate GaAs channel FET's     

Enhancement-mode power heterojunction FET utilizingAl0.5Ga0.5As barrier layer with negligibleoperation gate current for digital cellular phones

We have developed a novel enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET (HJFET) with a 5 nm thick Al_0.5Ga_0.5As barrier layer inserted between an In _0.2Ga_0.8As channel layer and an upper Al_0.2 Ga_0.8As electron supply layer. The Al_0.5Ga _0.5As barrier layer reduces gate current under high forward gate bias voltage, resulting in a high forward gate turn-on voltage (V _F) of 0.87 V, which is 170 mV higher than that of an HJFET without the barrier layer. Suppression of gate current assisted by a parallel conduction path in the upper electron supply layer was found to be also important for achieving the high V_F. The developed device exhibited a high maximum drain current of 300 mA/mm with a threshold voltage of 0.17 V. A 950 MHz PDC power performance was evaluated under single 3.5 V operation. An HJFET with a 0.5 μm long gate exhibited 0.92 W output power and 63.6% power-added efficiency with 0.08 mA gate current (I_g) at -48 dBc adjacent channel leakage power at 50 kHz off-center frequency. This I_g is one-thirteenth to that of the HJFET without the barrier layer. These results indicate that the developed enhancement-mode HJFET is suitable for single low voltage operation power applications     

Self-aligned shallow junction MJFET (metal junction FET) for higherturn-on and breakdown voltages

Simple self-aligned p⁺⁺-gate formation technology for a junction field-effect transistor (JFET) using elemental shallow Zn diffusion from patterned Au/Zn gate metal is reported. This diffusion technology makes it possible to control a very shallow p⁺⁺-layer less than 50 nm. The metal junction FET (MJFET) shows about 0.3 V higher gate turn-on voltage in forward bias and much larger reverse breakdown voltage than the conventional Al-gate MESFET with similar transconductances, typically 200 mS/mm for 1.5-μm gate length quasi-enhancement, and 90 mS/mm for 4-μm gate length deep depletion devices     

Ga2O3(Gd2O3)/InGaAsenhancement-mode n-channel MOSFETs

We have demonstrated the first Ga₂O₃(Gd₂O₃) insulated gate n-channel enhancement-mode In_0.53Ga_0.47As MOSFET's on InP semi-insulating substrate. Ga₂O₃(Gd₂ O₃) was electron beam deposited from a high purity single crystal Ga₅Gd₃O₁₂ source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-μm gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, f_t, and the maximum frequency of oscillation, f_max, of 7 and 10 GHz were obtained, respectively, for a 0.75×100 μm² gate dimension device at a gate voltage of 3 V and drain voltage of 2 V     

Metamorphic In0.4Al0.6As/In0.4Ga0.6As HEMTs on GaAs substrate

New In_0.4Al_0.6As/In_0.4Ga_0.6 As metamorphic (MM) high electron mobility transistors (HEMTs) have been successfully fabricated on GaAs substrate with T-shaped gate lengths varying from 0.1 to 0.25 μm. The Schottky characteristics are a forward turn-on voltage of 0.7 V and a gate breakdown voltage of -10.5 V. These new MM-HEMTs exhibit typical drain currents of 600 mA/mm and extrinsic transconductance superior to 720 mS/mm. An extrinsic current cutoff frequency f_T of 195 GHz is achieved with the 0.1-μm gate length device. These results are the first reported for In_0.4 Al_0.6As/In_0.4Ga_0.6As MM-HEMTs on GaAs substrate     

Diamond surface-channel FET structure with 200 V breakdown voltage

An enhancement mode diamond FET using a hydrogen-terminated surface as hole conductive channel has been fabricated with 200 V gate to drain breakdown voltage. At the 8.5-μm gate length the maximum drain current was 22 mA/mm. 90 mA/mm maximum drain current was obtained at a gate length of 3.0 μm. Scaling to below 1 μm gate length assuming undegraded breakdown conditions will result in a projected RF power handling capability above 6 W/mm     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

n+-polysilicon gate PMOSFET's with indium dopedburied-channels

In this letter a n⁺-polysilicon gate PMOSFET with indium doped buried-channel is discussed, The gate length scaling of n ⁺-polysilicon gate buried-length PMOSFET's is limited by the channel punch-through effect. Designing shallow counter-doped layers (buried-channels) has been established as a means to reduce the undesirable short channel effects in these devices. Indium, an acceptor dopant in Si, has a low diffusion coefficient and implant statistics favorable for achieving shallow doping layers. Indium implants are explored (as an alternative to BF₂) to counter dope the n-tub for adjusting the threshold voltage. Devices are fabricated using AT&T's 0.5 μm CMOS technology but with t_ox=50 Å. Although no special effort has been made to optimize the n-tub or to take full advantage of the diffusion and implant characteristics of indium, excellent electrical results are obtained for devices with L_eff=0.25 μm. Improved V_th roll-off characteristics and reduced body effect (γ≈0.18 V^½ versus γ_B≈0.40 V^½) in indium implanted buried channels are demonstrated over BF₂ implanted buried channels for PMOSFET's with identical long channel threshold voltages. The effects of incomplete ionization (freeze-out) of the indium acceptor states on the electrical device characteristics are demonstrated by device simulations and measurements     

High-breakdown characteristics of the InP-based heterostructurefield-effect transistor withIn0.34Al0.66As0.85Sb0.15Schottky layer

We report improved breakdown characteristics of InP-based heterostructure field-effect transistors (HFET's) utilizing In_0.34 Al_0.66As_0.85Sb_0.15 Schottky layer grown by low-pressure metalorganic chemical vapor deposition. Due to high energy bandgap and high Schottky barrier height (>0.73 eV) of the In_0.34Al_0.66As_0.85Sb_0.15 Schottky layer, high two-terminal gate-to-drain breakdown voltage of 40 V, three-terminal off-state breakdown voltage of 40 V three-terminal threshold-state breakdown voltage of 31 V, and three-terminal on-state breakdown voltage of 18 V at 300 K for In_0.75Ga_0.25As channel, are achieved. Moreover, the temperature dependence of two-terminal reverse leakage current is also investigated. The two-terminal gate-to-drain breakdown voltage is up to 36 V at 420 K. A maximum extrinsic transconductance of 216 mS/mm is obtained with a gate length of 1.5 μm     

Enhancement-mode Al0.66In0.34As/Ga0.67In0.33As metamorphic HEMT, modeling and measurements

This paper exhibits experimental and theoretical results on metamorphic high-electron mobility transistor (MM-HEMT). Modeling and measurements provide a better knowledge of device physics which allows us to optimize device structures. We present 10-GHz power performances, pulse and gate measurements, and two-dimensional (2-D) hydrodynamic modeling of enhancement-mode (E-mode) Al_0.66In_0.34As/Ga_0.67In_0.33 As NM-HEMT devices. It is the first time that cap layer thickness has been studied for a MM-HEMT. A typical reverse breakdown voltage of 16 V has been obtained. Gate current issued from impact ionization has been shown, for the first time, in such a device. The 2-D hydrodynamic model is a useful tool for cost engineering because it brings more information in terms of physical quantity distributions, necessary to predict breakdown behavior of FET. The 10-GHz measurements with a load-pull power set-up demonstrate the capabilities for a thick cap device with large gate-to-drain extension since an output power of 140 mW/mm have been obtained which is the state-of-the-art for such a device. These results obtained confirm the great interest of the structures for power application systems. The only work reported, to our knowledge, using a MM-HEMT structure in E-mode with an indium content close to 50% has been studied by Eisenbeiser et al.. Their typical gate-to-drain breakdown voltage was 5.2 V. The 0.6 μm ×3 mm devices exhibited 30 mW/mm at 850 MHz     

RF performance of diamond MISFETs

A cutoff frequency (f_T) of 11 GHz is realized in the hydrogen-terminated surface channel diamond metal-insulator-semiconductor field-effect transistor (MISFET) with 0.7 μm gate length. This value is five times higher than that of 2 μm gate metal-semiconductor (MES) FETs and the maximum value in diamond FETs at present. Utilizing CaF₂ as an insulator in the MIS structure, the gate-source capacitance is reduced to half that of the diamond MESFET because of the gate insulator capacitance being in series to the surface-channel capacitance. This FET also exhibits the highest f _max of 18 GHz and 15 dB of power gain at 2 GHz. The high-frequency equivalent circuits of diamond MISFET are deduced from the S-parameters obtained from RF measurement     

High-frequency performance of diamond field-effect transistor

The microwave performance of a diamond metal-semiconductor field-effect transistor (MESFET) is reported for the first time. MESFETs with a gate length of 2-3 μm and a source-gate spacing of 0.1 μm were fabricated on the hydrogen-terminated surface of an undoped diamond film grown by microwave plasma chemical vapor deposition (CVD) utilizing a self-aligned gate fabrication process. A maximum transconductance of 70 mS/mm was obtained on a 2 μm gate MESFET at V_GS=-1.5 V and V_DS=-5 V,for which a cutoff frequency f_T and a maximum oscillating frequency f_max of 2.2 GHz and 7 GHz were obtained, respectively     

Double-dopedIn0.35Al0.65As/In0.35Ga0.65As power heterojunction FET on GaAs substrate with 1 W outputpower

A double-doped metamorphic In_0.35Al_0.65As/In _0.35Ga_0.65As power heterojunction FET (HJFET) on GaAs substrate is demonstrated. The HJFET exhibits good dc characteristics, with gate forward turn on voltage of 1.0 V, breakdown voltage of 20 V, and maximum drain current of 490 mA/mm. Under RF operation at a frequency of 950 MHz, a power added efficiency of 63% with associated output power of 31.7 dBm is obtained at a gate width of 12.8 mm. This large gate width and state-of-the-art power performance in metamorphic HJFETS were enabled by a selective etching, sputtered WSi gate process and low surface roughness due to an Al_0.60Ga_0.40As_0.69Sb_0.31 strain relief buffer     

Enhancement mode metamorphicAl0.67In0.33As/Ga0.66In0.34As HEMT on GaAs substrate with high breakdown voltage

This paper presents original and experimental results provided by E-mode Al_0.67In_0.33As/Ga_0.66In_0.34 As metamorphic HEMT. The devices exhibit good dc and rf performances. The 0.4 μm gate length devices have saturation current density of 355 mA/mm at +0.6 V gate-to-source voltage. The Schottky characteristic is a typical reverse gate-to-drain breakdown voltage of -16 V. It is the first time, to our knowledge, that gate current issued from impact ionization have been observed in these devices versus gate to drain extension. These results are the first reported for E-mode Al _0.67In_0.33As/Ga_0.66In_0.34As MM-HEMTs on GaAs substrate     

High-temperature, high-voltage operation of pulse-doped diamondMESFET

The fabrication and operation of a pulse-doped diamond metal-semiconductor field-effect transistor (MESFET) is presented showing a usable source drain voltage of 70 V and no breakdown up to 100 V at 350°C operating temperature. A channel sheet concentration of 8.5×10¹² cm^-2 could be fully modulated leading to a maximum transconductance of 0.22 mS/mm, although full activation of the boron acceptor had not been reached. For an optimized device structure, with reduced gate length below 0.25 μm and full activation, more than 10 W/mm RF-power density can be predicted     

A possible scaling limit for enhancement-mode GaAs MESFETs in DCFLcircuits

A possible scaling limit for ion-implanted GaAs MESFETs with buried p-layer LDD structure has been numerically investigated. A Schottky-contact model with a thin interfacial layer and interface states was used to simulate the Schottky-barrier height of a scaled-down MESFETs. When enhancement-mode MESFETs in direct-coupled FET logic (DCFL) circuits are scaled down, the gate length can be reduced to 0.21 μm at an interface-state density of 6.6×10¹² cm^-2·eV^-1, when the barrier height is greater than 0.6 V, the threshold voltage is less than 0.1 V, and the channel aspect ratio is 8     

A GaAs MESFET with a partially depleted p layer for SRAMapplications

A GaAs MESFET with a partially depleted p layer that has a specific application to SRAMs has been developed. The short-channel effect is well suppressed for gate lengths down to 0.5 μm by a rather dense p layer buried under the channel. Its acceptor ion dose is as high as 2×10¹² cm^-2, which corresponds to a partially depleted condition. As for applications for SRAMs, it is possible to attain fully functional 7-ns 4-kb SRAMs that are operative at 75°C by using the FET with a 1-μm gate. A chip yield of 22% has been achieved in a 3-in wafer