一种软件级双轨逻辑的完整实现方案

旁路攻击是一种通过分析密码设备在运行时所产生的旁路信息来分析该密码设备的秘密信息的方法.Paul Kocher等人在1998年提出的功耗分析现在已经是针对密码设备的旁路攻击中非常常见的一种.在硬件实现的密码设备中,双轨逻辑是一种有效的抵抗功耗分析的方法,它通过用两位物理比特来表示一位逻辑比特,使数据0和1的表述对称,从而平衡了功耗的大小.对于软件实现的密码设备,也可以借鉴双轨逻辑的思路,这里给出了一个较为完备的软件级双轨逻辑方案,解决了一些前人方案的不周全指出,并之后在一个DES算法的实验中,验证方案的有效性.     

抗功耗攻击的随机插入式分组密码系统

近年来涌现出许多抗功耗分析的方法,例如双轨电路法、掩码法和随机操作插入法。仔细分析这些方法可以发现它们都有潜在的缺陷,这些缺陷使得这些方法大都受制于大量的数据统计(包括高阶数据统计)。提出了一种在分组密码加解密过程中加入伪轮函数的方法。伪轮函数的加入使得加解密过程具有不可重复性,从而给功耗分析带来很大的麻烦。用51单片机仿真了这个设计,并进行了相关的功耗分析,结果显示该设计能很好地抵制功耗分析。     

抗功耗攻击的逻辑电路研究

通过分析双轨电路的主要功耗泄露类型,评估了传统抗功耗攻击逻辑电路的安全性,指出其安全性漏洞。针对其漏洞,对LBDL电路进行改进,并提出了一种将改进后的电路与掩码技术相结合的MLBDL电路。Hspice仿真实验表明,MLBDL电路不仅能够消除由双轨信号布线差异引起的功耗泄露,而且能够消除由输入延时差异引起的功耗泄露,其抗功耗攻击能力显著增强。     

一种面向多媒体SOC的微状态低功耗设计方法

针对目前移动多媒体SOC设计中日益突出的功耗问题,结合传统的动态功率管理和动态频率调整中的负载预测和反馈控制两种方法,同时利用系统中各类IP和设计模块的可配置特性,提出了一种基于微状态的面向多媒体应用SOC的系统级低功耗设计方法。该方法以F-ARIMA过程作为负载预测模型,以最后期限缺失率作为反馈控制信号来实现系统实时动态在微状态之间进行切换,从而尽可能使得负载能均匀分布于运行期间。该方法在保证多媒体服务质量(QOS)的同时,有效降低了系统功耗。     

工艺偏差下基于功耗与延时的硬件木马检测有效性分析

首先简述了硬件木马以及现有的硬件木马检测方法,之后考虑了工艺偏差对硬件木马检测的影响;工艺偏差的存在对电路功耗和延时等都会造成一定的影响,从而在一定程度上掩盖了硬件木马电路引起的功耗和延时特征变化.实验中针对AES加密核心S-box电路设计植入了一种基于组合电路的功能型硬件木马电路,并在40 nm工艺下利用HSPICE模拟不同大小硬件木马电路下S-box电路功耗轨迹和延时数据,在不同工艺模式下分析基于功耗与延时检测木马的有效性.结果显示,基于延时的硬件木马检测方法在木马规模较小时更能有效实现硬件木马检测.当木马规模增大时,基于功耗的检测方法的优势更明显,其抗工艺偏差干扰的能力会更强.     

基于随机延时注入的跨时钟域信号验证方法

为了应对现代SOC复杂的时钟结构给跨时钟域信号处理带来的隐患,分析了跨时钟域信号产生的亚稳态现象的根本原因和常用的跨时钟域信号的处理方法,针对跨时钟域信号处理难以验证的问题,提出了基于随机延时注入的跨时钟域仿真验证方法.通过将亚稳态现象抽象成采样数据在时钟上的随机抖动,使得芯片设计的RTL前仿真在没有时钟树物理信息的情况下能够模拟出亚稳态效应.分析结果表明此方法能够完成SOC芯片的跨时钟域信号的功能验证.     

基于分形编码的图像压缩域检索

在小波域利用迭代分形码可以唯一表征原始编码图像特征的特点,由此可以利用迭代函数系统的某些特性实现基于分形压缩数据的图像检索操作.文中对基于迭代分形的图像压缩方法和检索方法进行了研究,在小波变换域内提出了一种基于迭代分形的高效图像压缩方法.同时在图像分形码的基础上利用迭代函数系统的分布特性来进行图像间相似距离的计算,从而实现了基于分形压缩数据的图像检索操作.     

一款低功耗异步FIFO的设计与实现

我们在异步FIFO(First In First Out)设计中,引入了门控时钟技术降低了控制电路和译码电路 80%的功耗;并采用位线分割技术降低了存储单元38%的功耗.利用格雷码作异步FIFO指针的控制电路,能有效消除多时钟域中的亚稳态.基于CSMC 0.6 μm标准单元库的半定制设计流程对其进行设计和实现:使用Verilog硬件描述语言,利用Modelsim进行时序和功能仿真、Synopsys DC完成逻辑综合、SE实现自动布局布线.     

基于翻转信息熵的组合逻辑电路功耗分析

基于信息熵的复杂度分析方法是在VLSI设计流程的高层次抽象阶段对组合逻辑电路功耗和面积进行分析估计的可行方法之一.本文通过提出新的利用翻转信息熵进行电路实现面积和功耗估计的理论方法,改善了面积和功耗估计精度.大量基于随机电路和BENCHMARK电路的实验结果表明,上述方法能够使面积和功耗估计的相对误差分别降低24.3% (从12.74%到9.65%)和15.4% (从13.67%到11.57%).     

SCSI冗余路径软件的研究与实现

在主机系统和存储系统之间增加冗余SCSI路径,并在主机上运行SCSI路径管理软件,从而在SCSI路径之间实现负载均衡和故障切换,并讨论了在Windows NT系统下SCSI路径管理软件的原理和实现方法.     

一种新的无电解电容Led驱动电源设计

传统的LED驱动电源由于有电解电容的存在,制约了LED照明技术的应用领域。针对此问题,提出了一种通过变压器和电容之间进行能量转化的电路,从而减少电容容量,实现由贴片电容取代大容量电解电容的方法,实验结果表明该方法的可行性。     

基于NCL路径平衡的抗功耗分析方法

由于对路径结构平衡的本质以及设计方法缺乏系统的研究,导致其在实际应用中严重依赖设计者自身的经验,难以推广到各类自动化综合方法中。对实现路径平衡结构的形式化定义及充分条件进行了研究,并给出了证明,进而提出了一种基于改进二元决策图(BDD, binary decision diagram)的零协议逻辑(NCL, null convention logic)异步电路路径平衡扩展方法。该方法能够简便地扩展至各类自动化综合过程中,并能在不改变目标电路特性的前提下,有效实现NCL异步电路的路径平衡结构,抵消由于寄生电容和负载电容差异所造成的密码芯片旁路信息泄露。     

红外焦平面器件开窗寻址电路的设计

基于可综合风格的Verilog HDL技术,采取控制单元与数据通道分离的设计结构,对320×256红外焦平面阵列的开窗寻址电路进行RTL级建模,设计了具有对红外焦平面阵列任意开窗寻址功能和读出顺序可上下左右翻转功能的寻址电路。并在Cadence NC Verilog环境下进行编译与仿真,仿真结果表明整个设计能够实现预期寻址功能,满足IRFPA读出多样化的需求。     

A novel high-performance voltage regulator for single-phase ACsources

Regulation of load voltage in single-phase applications is becoming an important issue for critical loads. This paper presents a novel high-performance single-phase voltage regulator which has a common arm between the rectifier and inverter, and adopts an appropriate switching strategy. The proposed voltage regulator employs six switches and can be implemented by only one three-phase inverter module. The proposed voltage regulator has the capability of delivering sinusoidal input current with unity power factor, good output voltage regulation, and bidirectional power flow. For these purposes, a fully digital controller is designed and implemented using a TMS320F240 digital signal processor. In addition, a novel low-cost AC capacitor is also presented. This type of capacitor requires two DC capacitors and two diodes, enabling low-cost and compact manufacturing. Consequently, the complete voltage regulator system, which is mainly suitable for an uninterruptible power supply as well as reactive or nonlinear loads, can be constructed compactly and inexpensively. Experimental results are presented to verify the feasibility of the proposed voltage regulator system     

A high-efficiency charge pump with charge recycling scheme and finger boost capacitor

A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency and it is implemented in a 0.35 μm high-voltage CMOS IC technology. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. By combining the charge recycling method and the finger capacitor, the proposed four-stage charge pump can achieve an efficiency of 47.2% and an output voltage of 13.7 V from a 3 V power supply. The proposed charge pump also has better current driving ability and the area of the chip is 2.32 mm × 0.28 mm.     

Power-efficient metastability error reduction in CMOS flash A/Dconverters

A power and area efficient technique to reduce metastability errors in high-speed flash A/D converters is described. Pipelining to reduce error rates in an n-bit flash converter is accomplished with a bit pipeline scheme requiring n latches per pipeline stage instead of 2 ⁿ-1. A 7-b, 80 MHz prototype converter is implemented in 1.2-μm CMOS with measured metastability error rates of less than 10 ^-12 errors/cycle. The measured power is 307.2 mW with an 80-MHz sampling frequency. Without metastability error reduction circuitry, the estimated metastability error rate for the converter is 10^-4 errors/cycle. Achieving an equivalent error rate with two pipeline stages of 2ⁿ-1 latches would require 3.48 times the power for the metastability error reduction circuitry. This corresponds to a reduction in total power by a factor of 1.24 compared with the comparator pipelined converter for Nyquist frequency inputs     

A novel all-optical label swapping based on RZ-DQPSK/IRZ-ASK combined modulation format

A novel all-optical label swapping based on optical return zero (RZ) differential quadrature phase shifted keying/inverse return zero amplitude shifted keying (RZ-DQPSK/IRZ-ASK) combined modulation format scheme is investigated and analyzed theoretically. Internet protocol (IP) packets can be efficiently labeled and processed using this proposed scheme. Numerical simulation is taken to demonstrate the transmission characteristic of the all-optical label swapping based on RZ-DQPSK/IRZ-ASK modulation format. The transmission performance can be affected by the duty cycle of the IRZ pulse, the IRZ-ASK label extinction ratio, the dispersion compensation ratio, received optical power and the coupling coefficient of the coupler. Results show that the IRZ-ASK label extinction ratio is almost infinite and preferable performance is obtained. The proposed scheme is a practical solution to meet the data rate and cost-efficient of the optical links simultaneously in tomorrow's all-optical label swapping.     

SOC中Data-Path布图设计面临的挑战

目前所设计的系统级芯片(SOC)包含有多个data-path模块,这使得data-path成为整个G大规模集成电路(GSI)设计中最关键的部分.以往的布图理论及算法在许多方面已不能满足data-path布图设计的需要,这主要是由于传统的布图工具没有考虑data-path所特有的电路结构特点.Data-path具有规整的位片结构,具有很高的性能指标要求,如对于时延、耦合效应和串扰等性能都有严格的要求.此外,data-path中还存在大量成束状结构的BUS线网.文中提出了data-path布图设计所面临的挑战.从介绍data-path布图的基本问题入手,重点分析了data-path布图设计中的关键技术,并在讨论已有研究工作的基础上针对不同的布图阶段提出了可行的技术路线与设想.     

Tunable Capacitor Based on Polymer-Dispersed Liquid Crystal for Power Harvesting Microsystems

A tunable capacitor based on polymer-dispersed liquid-crystal (PDLC) technology is presented in this paper. Its application for robust power harvesting microsystems was investigated. The power harvesting device utilized a piezoelectric microcantilever excited by ambient random vibrations to convert mechanical energy into electric power. For improving the power harvesting efficiency, the PDLC tunable capacitor was used to adjust the resonance frequency of the piezoelectric microcantilever beam to match the frequency of the ambient vibrations in real time. The fabrication process and measurement results of the PDLC tunable capacitor are detailed. The measured tuning ratio of the PDLC tunable capacitor was 63% at 300-Hz excitation frequency when a 25-V driving voltage was applied. The dielectric and optical properties of the fabricated PDLC tunable capacitor have been examined thoroughly. Based on the results of the experiment, an equivalent lumped-element model of the PDLC tunable capacitor has been developed. The simulation results showed that the impedance of the developed model agreed well with that of the fabricated tunable capacitor. This model can be incorporated into the equivalent circuit of the integrated power harvesting system for efficiency optimization.     

基于PSpice的光伏并网系统仿真研究

采用DC／DC和DC／AC两级拓扑结构对光伏并网系统进行了研究和设计,采用改进的定电压跟踪法（CVT）实现最大功率点闭环跟踪,并将PWM控制器引入并网逆变中,采用三角波比较方式实现SPWM电压逆变和输出电流的波形跟踪与控制,在电压、电流内环的基础上引入功率外环以实现系统前后级功率平衡和能量管理,采用基于PSpice的光伏电池仿真模型对所设计光伏并网系统进行了仿真。仿真结果表明,基于PSpice的光伏仿真模型能够有效地模拟实际光伏并网系统的行为特征,将PSpice软件用于光伏发电系统的仿真是可行的。