A comparison of hydrogen and deuterium plasma treatment effects onpolysilicon TFT performance and dc reliability

We compare the performance and dc reliability of conventional top-gate, self-aligned polysilicon (poly-Si) thin-film transistors (TFT's) after passivation by plasma deuteration and conventional plasma hydrogenation. An optimum deuteration temperature of 300°C is found, as compared to 350°C for hydrogenation. Deuteration yields comparable TFT performance as hydrogenation, while deuterated TFT's exhibit increased resistance to threshold voltage degradation under dc stress. These results indicate that deuteration is a promising alternative to hydrogenation for achieving high-performance, high-reliability poly-Si TFT's for applications such as flat-panel displays     

A novel lightly doped drain polysilicon thin-film transistor withoxide sidewall spacer formed by one-step selective liquid phasedeposition

We have proposed and successfully demonstrated a novel process for fabricating lightly doped drain (LDD) polycrystalline silicon thin-film transistors (TFT's). The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) oxide performed at 23°C. Devices fabricated with the new process exhibit a lower leakage current and a better ON/OFF current ratio than non-LDD control devices. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be quite promising for future high-performance poly-Si TFT fabrication     

Low-frequency noise characteristics of UHV/CVD epitaxial Si- andSiGe-base bipolar transistors

We report the first measurements of low-frequency noise in high-performance, UHV/CVD epitaxial Si- and SiGe-base bipolar transistors. The magnitude of the noise power spectral density at fixed frequency for both Si and SiGe devices is comparable for similar bias, geometry, and doping conditions, indicating that the use of strained SiGe alloys does not degrade transistor noise performance. The best recorded values of noise corner frequency were 480 Hz and 373 Hz for the Si and SiGe transistors, respectively, for multi-stripe devices with an emitter area of 0.5×10.0×3 μm². A functional dependence of the noise power spectral density on base current for both device types of I_B^1.90 was observed, and noise measurements as a function of device geometry suggest that the contributing noise sources are uniformly distributed across the emitter of the transistors, not at the emitter periphery     

Self-heating and kink effects in a-Si:H thin film transistors

We describe a new physics based, analytical DC model accounting for short channel effects for hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT's). This model is based on the long channel device model. Two important short-channel phenomena, self-heating and kink effects, are analyzed in detail. For the self-heating effect, a thermal kinetic analysis is carried out and a physical model and an equivalent circuit are used to estimate the thermal resistance of the device. In deriving the analytical model for self-heating effect, a first order approximation and self-consistency are used to give an iteration-free model accurate for a temperature rise of up to 100°C. In the modeling of the kink effects, a semi-empirical approach is used based on the physics involved. The combined model accurately reproduces the DC characteristics of a-Si:H TFT's with a gate length of the 4 μm. Predictions for a-Si:H TFT's scaled down to 1 μm are also provided. The model is suitable for use in device and circuit simulators     

Benefits of XPS nanocharacterization for process development and industrial control of thin SiGe channel layers in advanced CMOS technologies

The Si channel of advanced p-type transistors has been replaced by a compressively strained Silicon-Germanium channel (SiGe) in order to improve the device performances. The SiGe thickness and composition must be precisely controlled to reproducibly obtain the same characteristics. In this study, the benefits of X-ray Photoelectron Spectroscopy (XPS) for the process development and the industrial control of thin SiGe channel layers are shown. The use of a parallel Angle Resolved XPS (pARXPS) allowed us to obtain the germanium distribution in very thin SiGe channels, a useful information to better understand the impact of various process steps on the germanium distribution. The hybridization of in-line XPS and X-Ray Reflectivity (XRR) has been used as an industrial process control characterization method to jointly determine the SiGe channel's thickness and germanium composition. This hybrid industrial metrology technique has shown promising results.     

SiGe-channel heterojunction p-MOSFET's

The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET's) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET's. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n⁺ polysilicon-gate SiGe p-MOSFET's have acceptable short-channel behavior at 0.20 μm channel lengths and are preferable to p⁺ polysilicon-gate p-MOSFET's for 2.5 V operation. Experimental results of n⁺-gate modulation-doped SiGe p-MOSFET's illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm² /V.s at 300 K and 980 cm²/V.s at 82 K are obtained     

Visualizing the doping profile of a silicon germanium HBT with polysilicon emitter using electron holography

Modern bipolar transistors use polysilicon emitters and an epitaxial grown silicon germanium (SiGe) base. For device optimization, both the SiGe base and the region of the diffused emitter is of special interest. In this paper, electron holography is applied to visualize and directly measure the two-dimensional distribution of the local potential in a high-performance SiGe heterojunction bipolar transistor. Special emphasis is put on investigating the region of the emitter diffused into the epitaxially grown base layer. In addition, we investigate the self-aligned base-link construction. We compare electron holographic measurements of the whole transistor to secondary ion mass spectrometric (SIMS) data and discuss the results.     

Controlled two-step solid-phase crystallization forhigh-performance polysilicon TFT's

Solid-phase crystallization for polysilicon thin-film transistors (TFT's) is generally limited by a tradeoff between throughput and device performance. Larger grains require lower crystallization temperatures, and hence, longer crystallization times. In this letter, a novel crystallization technique is presented which increases both throughput and device performance, using a two-step process, controlled using an in situ acoustic temperature/crystallinity sensor. A high-temperature rapid thermal annealing (RTA) nucleation step is followed by a low-temperature grain growth step to grow large-grain polysilicon. TFT's have been fabricated with a substantial improvement in throughput and device performance. This promises a high-throughput, high-performance, spatially uniform TFT process     

High-performance laser-processed polysilicon thin-film transistors

We present electrical results from hydrogenated laser-processed polysilicon thin-film transistors (TFT's) fabricated using a simple four-mask self-aligned aluminum top-gate process. Transistor field-effect mobilities of 280-450 cm²/Vs and on/off current ratios of more than 10⁸ are measured in these devices. Except for the amorphous-silicon deposition step, the highest processing temperature that the substrate was subjected to was 350°C. Such good performance is attributed to an optimized laser-crystallization process combined with hydrogenation     

The electrostatic charging damage on the characteristics andreliability of polysilicon thin-film transistors during plasmahydrogenation

In this letter, the impacts of electrostatic charging damage on the characteristics and gate oxide integrity of polysilicon thin-film transistors (TFT's) during plasma hydrogenation were investigated. Hydrogen atoms can passivate trap states in the polysilicon channel, however, plasma processing induced the effect of electrostatic charging damages the gate oxide and the oxide/channel interface. The passivating effect of hydrogen atoms is hence antagonized by the generated interface states. TFT's with different area of antennas were used to study the damages caused by electrostatic field     

CMOS and SiGe bipolar circuits for applications up to 110 GHz

Recently, CMOS has been demonstrated to be a viable technology for very-high-bit-rate broad-band and wireless communication systems up to 40 Gb/s and 50 GHz. Advances in device scaling and doping-profile optimization have also resulted in SiGe bipolar transistors with impressive performance, including cut-off frequencies of more than 200 GHz. This paper presents advances in circuit design which fully exploit the high-speed potential of a 0.13 µm CMOS technology up to 50 GHz and of a high-performance SiGe bipolar technology up to 110 GHz operating frequency. The combination of advanced circuit techniques and a state-of-the-art fabrication-process technology results in continuing the upward shift of the frequency limits.     

High-performance thin-film transistors in low-temperature crystallized LPCVD amorphous silicon films

Thin-film transistors (TFT's) were fabricated in low-temperature (550°C) crystallized amorphous LPCVD silicon films. The performance of these devices was found to depend upon the deposition temperature. Low threshold voltages and effective mobilities as high as 32 cm²/V.s are reported for devices fabricated in 150-nm-thick films with maximum processing temperature of 860°C. The performance of these devices is shown to be far superior to devices fabricated in as-deposited polycrystalline silicon films.     

Neutral base recombination and its influence on the temperaturedependence of Early voltage and current gain-Early voltage product inUHV/CVD SiGe heterojunction bipolar transistors

We present the first comprehensive investigation of neutral base recombination (NBR) in ultra-high vacuum/chemical vapor deposited (UHV/CVD) SiGe heterojunction bipolar transistors (HBT's), and its influence on the temperature characteristics of Early voltage (V_A ) and current gain-Early voltage product (βV_A). We show that a direct consequence of NBR in SiGe HBT's is the degradation of V_A when transistors are operated with constant-current input (forced-I_B) as opposed to a constant-voltage input (forced-V_BE). In addition, experimental and theoretical evidence indicates that with cooling, V_A in SiGe HBT's degrades faster than in Si bipolar junction transistors (BJT's) for forced-I_B mode of operation. Under the forced-V_BE mode of operation, however, SiGe HBT's exhibit a thermally-activated behavior for both V_A and βV_A, in agreement with the first-order theory. The differences in V_A as a function of the input bias and temperature for SiGe HBT's are accurately modeled using a modified version of SPICE. The performance of various practical SiGe HBT circuits as a function of temperature, in the presence of NBR, is analyzed using this calibrated SPICE model     

Strained ${rm n}$-MOSFET With Embedded Source/Drain Stressors and Strain-Transfer Structure (STS) for Enhanced Transistor Performance

A novel-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current I_DSAT improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.     

Novel gate dielectric films formed by ion plating forlow-temperature-processed polysilicon TFTs

A novel SiO₂ film formed by ion plating (IP) at room temperature was developed for low-temperature-processed (LTP) (<625°C) polysilicon thin-film transistors (poly-Si TFT's). The IP SiO₂ film is a high-density dielectric with strained bonds, and also a high-performance insulator with low-leakage current and high-breakdown voltage. Poly-Si TFT with IP SiO₂ as a gate insulator shows satisfactory performance     

Pentacene organic thin-film transistors-molecular ordering andmobility

Pentacene-based organic thin-film transistors (TFT's) with field-effect mobility as large as 0.7 cm²/V·s and on/off current ratio larger than 10⁸ have been fabricated. Pentacene films deposited by evaporation at elevated temperature at low-to-moderate deposition rates have a high degree of molecular ordering with micrometer-sized and larger dendritic grains. Such films yield TFT's with large mobility. Films deposited at low temperature or by flash evaporation have small grains and poor molecular ordering and yield TFT's with low mobility     

Low frequency noise in SiGe-base heterojunction bipolar transistors and SiGe-channel metal oxide semiconductor field effect transistors

We show that low frequency noise (LFN) in SiGe-base heterojunction bipolar transistors and SiGe-channel pMOSFETs may be made significantly lower than that in their all-Si counterparts and indicate how this can be done. Optimization of LFN in SiGe channel pMOSFETs follows from a calculation involving a novel analytical model, which accounts for both static and LFN characteristics of SiGe-channel devices.     

Performance improvement obtained for thin-film transistorsfabricated in prepatterned laser-recrystallized polysilicon

Thin-film transistors (TFT's) are fabricated in polysilicon films that are laser recrystallized either before or after active-area definition. We find the the performance of TPT's fabricated in active areas that are prepatterned before laser recrystallization is dramatically improved. For example, the field-effect mobility is increased by a factor of three, the threshold voltage is reduced from 5.32 V to 0.07 V, and the subthreshold slope is cut in half for W/L = 10 μm/10 μm TFT's. All TFT's discussed utilize gas-immersion laser-doped source and drain junctions and are unhydrogenated     

Control of the Morphology and Structural Development of Solution‐Processed Functionalized Acenes for High‐Performance Organic Transistors

Solution‐processable functionalized acenes have received special attention as promising organic semiconductors in recent years because of their superior intermolecular interactions and solution‐processability, and provide useful benchmarks for organic field‐effect transistors (OFETs). Charge‐carrier transport in organic semiconductor thin films is governed by their morphologies and molecular orientation, so self‐assembly of these functionalized acenes during solution processing is an important challenge. This article discusses the charge‐carrier transport characteristics of solution‐processed functionalized acene transistors and, in particular, focuses on the fine control of the films' morphologies and structural evolution during film‐deposition processes such as inkjet printing and post‐deposition annealing. We discuss strategies for controlling morphologies and crystalline microstructure of soluble acenes with a view to fabricating high‐performance OFETs.     

Impact of device geometry and doping strategy on linearity and RF performance in Si/SiGe MODFETs

Based on careful calibration in respect of 70 nm n-type strained Si channel Si/SiGe modulation doped FETs (MODFETs) fabricated by Daimler Chrysler, numerical simulations have been used to study the impact of the device geometry and various doping strategies on device performance and linearity. Both the lateral and vertical layer structures are crucial to achieve high RF performance or high linearity. The simulations suggest that gate length scaling helps to achieve higher RF performance, but degrades the linearity. Doped channel devices are found to be promising for high linearity applications. Trade-off design strategies are required for reconciling the demands of high device performance and high linearity simultaneously.