应用于26 GHz-41 GHz频率综合器的高速可编程分频器的设计

毫米波频率综合器中的重要模块之一高速可编程多模分频器,它主要用于对VCO的输出信号进行分频从而获得稳定的本振信号,它的性能影响整个毫米波频率综合器性能。本文设计的一种高速、低功耗、分频比可变的分频器具有非常重要的意义[1]。根据26 GHz-41 GHz硅基锁相环频率综合器的系统指标,本文基于TSMC 45nm CMOS工艺,设计实现了一种高速可编程分频器。本文采用注入锁定结构分频结构实现高速预分频,该结构可以实现在0 d Bm的输入功率下实现25 GHz-48 GHz的分频范围、最低功耗为:2.6 m W。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器组成。其中8/9双模分频器由同步4/5分频器和异步二分频构成,工作频率范围10 GHz-27 GHz,最低输入幅度为:300 m V,最低功耗为:1.6 m V。可编程吞咽计数器采用改进型带置数功能的TSPC D触发器,该可编程分频器的最大工作范围:25 GHz;最小功耗为:363μW。本文设计的高速可编程多模分频器,可以实现32-2 062的分频比;当工作于28 GHz时,相位噪声小于-159 dBc/Hz。动态功耗为5.2 m W。     

Wide division ratio range programmable frequency divider with close-to-50% output duty-cycle

A novel wide division ratio (DR) range programmable frequency divider is presented in this article, which is based on the proposed divide-by-2/3/4 cell. The divider's output is buffered by a divide-by-2 cell; hence, it can achieve the close-to-50% output duty-cycle. The DRs can be set via the convenient provisions of binary bits. When the DR is even, the output duty-cycle is exactly 50%. If the DR is odd, the output duty-cycle is k/(2?k?+?1), where k is a natural number, therefore, it becomes close-to-50% with an increasing k. A divider with eight DR control bits, which can realise the DRs from 8 to 511, is implemented in standard 0.18?µm complementary metal-oxide semiconductor technology, the die area is 0.02?mm². The measured results show that the divider can obtain 44.4–50% output duty-cycle which corroborates with the calculation.     

A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers

A high-frequency divide-by-256–271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchronous counters. The programmable divider using proposed flip-flops is measured in 0.25-μm CMOS technology with the operating clock frequency reaching as high as 4.7 GHz under the supply voltage of 3V.     

58.8/39.2 GHz dual-modulus CMOS frequency divider with 9.2x5.2 /spl mu/m core size

A 58.8/39.2 GHz dual-modulus inductor-less frequency divider is proposed. The divider was fabricated using 90 nm CMOS with 9.2times5.2 mum core size. As a result, without using an inductor, the operating frequency was 40 GHz in the divide-by-2 mode and 59 GHz in the divide-by-3 mode at a power-supply voltage of 1.15 V with a power consumption of 1.2 mW     

On the injection methods in a top-series-injection-locked frequency divider

This paper proposes a top-series-injection-locked frequency divider (ILFD) with a tunable active inductor with variable division ratio and studies the effect of injection methods on the property of ILFD. With only the differential injection method the ILFD has the modulus of 1, 2, 3, 4, and 5. The ILFD was fabricated in the 0.18 μm 1P6M CMOS technology, and at the supply voltage of 1.5 V, the free-running divider is tunable from 0.13 GHz to 2.93 GHz. The ILFD has wide-operation locking ranges in both divide-by-2 and divide-by-3 mode.     

High-speed and low-power GaAs DCFL divider

High-speed and low-power divide-by-252 or -256 circuit have been fabricated by using high-transconductance GaAs enhancement-mode MESFETs. This variable-modulus divider is able to operate up to a clock frequency of 3.7 GHz. The total power dissipation at the maximum frequency is 180 mW, and it is as low as 42 mW and 30 mW at 3 GHz and 2.5 GHz, respectively.     

10～37GHzCMoS四分频器的设计

给出基于0．13μmCMOS工艺、采用单时钟动态负载锁存器设计的四分频器。该四分频器由两级二分频器级联而成。级间采用缓冲电路实现隔离和电平匹配。后仿真结果表明其最高工作频率达37GHz,分频范围为27GHz。当电源电压为1．2V、工作频率为37GHz时,其功耗小于30mW,芯片面积为0．33-0．28mm2。     

39.5-GHz static frequency divider implemented in AlInAs/GaInAs HBTtechnology

A static divide-by-4 frequency divider operating at 39.5 GHz with a corresponding gate delay of 12.6 ps was implemented using InP-based HBT technology. The AlInAs/GaInAs HBT devices utilized in the divider incorporated a graded emitter-base (E-B) junction and had a unity gain cutoff frequency, maximum frequency of oscillation, and current gain β of 130 GHz, 91 GHz, and 39, respectively. The divider was operated with a 3-V power supply and consumed a total power of 425 mW (77 mW per flip-flop). The divider functional yield was over 90%. The operating frequency of this circuit is the highest ever reported for a static divider     

Experimental evaluation of hot-carrier stressed series-tuned injection-locked frequency divider

This paper, for the first time, investigates hot carrier effect on a divide-by-2 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the series-resonant resonator. It is shown that the locking range decreases and the oscillation frequency increases with stress time, and the phase noise in both the free-running and locked state increases with stress time. The measured operation range after RF stress also shows degradation from the fresh circuit condition.     

1 V 10 GHz CMOS frequency divider with low power consumption

A low supply voltage and low power ultra-high frequency divider is investigated. The proposed inverter of the frequency divider is able to operate at higher frequencies with enhanced output voltage swing and lower power consumption under an ultra-low supply voltage compared to that of existing divide-by-2 units. The frequency divider implemented with this inverter using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 10 GHz for a 1 V supply voltage with 1.3 mW power consumption.     

An InGaAs/InP 40 GHz CML static frequency divider

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology’s ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2:1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic(CML) with 30 transistors.The circuit operated at a peak clock frequency of 40 GHz and dissipated 650 mW from a single -5 V supply.     

Wide locking range divide-by-4 LC-tank injection-locked frequency divider using series-mixers

A novel wide locking range divide-by-4 injection-locked frequency divider (ILFD) is proposed in this paper and was implemented in the TSMC 0.18 μm 1P6 M CMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator with a parallel-tuned LC resonator and two mixers in series to serve as an injection device. At the drain-source bias of 0.8 V and at the incident power of 0 dBm, the locking range of the divide-by-4 is 1.7 GHz, from the incident frequency 10.3–12.0 GHz, and the percentage of locking range is 15.25 %. The core power consumption is 11.98 mW. At drain-source voltage of 0.9 V, the locking range of the divide-by-4 is 2 GHz, from the incident frequency 10.1–12.1 GHz, and the percentage is 18.0 %. At drain-source voltage of 1.0 V, the locking range is 2.2 GHz (20.0 %) from 9.9 to 12.1 GHz. The die area is 0.492 × 0.819 mm².     

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer.The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively.Using a DMP high speed,lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps.The flexibility and reusability of the programmable divider is high;its use could be extended to many complicated frequency synthesizers.By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.     

Divide-by-2 injection-locked frequency divider implemented with two shunt 4th-order LC resonators

A triple-band divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4th order LC resonators to form a 6th order resonator with three resonant frequencies. Measured data has shown that the ILFD has three locking ranges at fixed bias condition or by varactor bias switching.     

40GHz InGaAs/InP CML 结构静态分频器

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology's ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2:1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic(CML) with ...     

数模混合GHz级频率综合器下变频模块设计

介绍了一种应用于GHz级高速频率合成器的数模混合下变频模块.采用了高速射频双模预分频器与数字逻辑综合生成的可编程吞脉冲分频器相结合的设计方法.双模预分频实现了高速低抖动低功耗,双模预分频器工作在除8状态输出133MHz频率时,均方差抖动小于2ps;可编程吞脉冲分频器算法灵活、设计复用性强,该算法可以灵活运用到许多复杂频率综合系统.相比较而言,该设计获得了更好的高频电路性能与设计复用性.     

A power-efficient 14.8-GHz CMOS programmable frequency divider with quadrature outputs in 40-nm CMOS process

This paper presents a power-efficient CMOS frequency divider (FD) with wide-band programmable division ratio and quadrature outputs for high-speed data transmission applications. The proposed FD consists of a power-efficient programmable divider (PD), a complementary volt-age-to-time converter based duty-cycle correction circuit, and a compact quadrature divider (QD). In the chain of PD, a sense-amplifier based dynamic flip-flop is proposed for 2/3 divider cell to achieve high-speed operation with significantly reduced power consumption. In addition, a simple but effective QD based on two pseudo-differential voltage-controlled tri-state inverters, is beneficial for generating precise quadrature output signals. Measurement results in 40-nm CMOS process show that the proposed FD achieves a wide division range from 16 to 254 and operates up to 14.8 GHz while consuming the power of 540.6 μW at 1.1-V supply, and occupying the active area of 0.00267 mm² (114.6 μm × 23.3 μm).     

A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS

A 5.3-GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D-flip-flop (DFF). An improved glitch-free phase switching architecture through the use of retimed multiplexer control signals is introduced. A high-speed low-voltage DFF circuit is given. The programmable divider fabricated in 0.25-μm technology occupies 0.09 mm²; it consumes 17.4 mA at 1.8 V and 26.8 mA at 2.2 V. Operation of 5.5 GHz with 300-mV_pk single-ended input is achieved with a 2.2-V supply. The residual phase noise at the output is -131 dBc/Hz at an offset of 1 kHz from the carrier while operating from a 5.5 GHz input     

集总元件宽带Wilkinson功分器的研究

提出了一种集总元件宽带Wilkinson功分器的分析及设计方法。从功分器的奇偶模阻抗理论分析出发,将功分器设计转化为在偶模下求解阻抗比为2:1的宽带阻抗变换和在奇模下求解宽带阻抗匹配的问题,采用LC阻抗变换节取代传统电路的λ/4传输线,减小功分器体积,并推导出两级功分器的元件解算公式。经ADS仿真验证,由解算公式得到的两级功分器,在760～1240MHz的带宽内功率分配损耗小于0.1dB,隔离度大于20dB,输入输出端口反射系数均小于-20dB,可用带宽fH/fL为1.64,实现了Wilkinson功分器小尺寸、带宽大的优点。     

A 125 GHz millimeter-wave phase lock loop with improved VCO and injection-locked frequency divider in 65 nm CMOS process

In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz) by applying?±?1.2 V input voltage variation. The divide-by-4 ILFD circuit uses a cross coupled VCO with three injection transistors acting in linear and nonlinear regions. The frequency dividers such as divided-by-4 ILFD, subsequent current mode logic (CML) and true single phase clock (TSPC) as divider chain with ratio 1/256 are used to synthesize frequency 244 MHz which is compared to reference frequency, 244 MHz in the PLL. Simulation results of the proposed PLL circuit are obtained after extracting post layout (with total chip size of 0.29 mm²) in 65 nm CMOS standard technology and @ 1.2 V power supply voltage. The obtained results confirm theoretical relations and indicate that the proposed circuit has good figure of merit (FoM), and higher tuning range and lower die area than the recent designs.