CMOS集成电路应用讲座——第三讲 CMOS门电路的应用

CMOS电路由于功耗低、输入阻抗高、电源电压范围宽、噪声余量大等优点,因而特别适合于各种数字电路系统.在系统中往往需要各种振荡器、单稳态电路等基础电路,本讲座主要是以实用的例子来说明各种基础电路的组成方法.一简单门电路的灵活应用(一)振荡器1.双门振荡器图1为由二个反相器组成的多谐振荡器,反相器可以用CO33六反相器或其他门电路组成,是一种常用的方波振荡器.     

非对称式多谐振荡器的Multisim仿真

针对Multisim中器件从0输出状态开始仿真,仿真非对称式多谐振荡器工作波形不能形成振荡输出,提出了在仿真电路的输入端接入转换开关,仿真时先将转换开关接地使电路脱离系统设置的初始输出状态,再通过转换开关构成非对称式多谐振荡器,进行正常工作状态的仿真.特点是直观形象地描述了多谐振荡器的工作工程、解决了多谐振荡器工作波形无法用电子实验仪器进行分析验证的问题.     

多谐振荡器的研究与仿真

分析了各种多谐振荡器的电路结构及工作原理，并利用Multisim10．0对部分电路进行了仿真，重点介绍了单稳型多谐振荡器，讨论集成单稳态触发器74121定时元件RC对暂稳态的影响以及单稳型多谐振荡器的应用。Multisim软件是一种形象化的虚拟仪器电路仿真软件，它能比较快速地模拟、分析、验证所设计电路的性能，在课堂教学中引入EDA技术，使传统教学环节与先进的仿真技术相结合，实现授课的生动性和灵活性，增强学生对基本概念的理解，激发学生的学习兴趣，培养并有效提高学生综合分析、应用及创新能力。     

射频连续波对多谐振荡器的干扰研究

在GTEM室中用射频连续波对某导弹装备上的一块数字控制电路进行电磁辐照实验,在一定的场强下,产生控制信号的自激多谐振荡器受到了电磁干扰,主要表现为产生的方波控制信号占空比增大。分析了多谐振荡器受干扰的机理,用电路仿真软件对多谐振荡器受到的干扰进行了模拟,验证了对干扰机理的分析。     

多谐振荡器电路集锦

自激多谐振荡器接通电源后,不需要外加触发脉冲,就能自动振荡,产生矩形脉冲。由于矩形脉冲含有极其丰富的谐波成分,所以产生这种波形的电路称为多谐振荡器,由于其没有稳定状态,故又称为无稳态多谐振荡器。多谐振荡器在数字电路中常常作为脉冲信号源,其电路类型是灵活和多种多样的。本文介绍八种多谐振荡器电路。一、用同型号三极管组成的多谐振荡器     

门电路环形振荡器仿真研究

在测量门电路的传输延迟时间时,通常用门电路环形振荡器,但门电路环形振荡器振荡频率较高,对实验仪器设备的要求也较高,用仿真实验的方法有直观明了的优点,所以在数字电路教学中常用仿真的方法来进行实验.然而,在用仿真方法进行实验分析时,实验结果和实物实验或理论分析会存在一些差异.分别用EWB的2种版本仿真软件EWB 5和Multisim 9对门电路环形振荡器进行仿真,分析出现差异的原因,指出在用仿真方法进行数字电路仿真分析和设计时要注意的问题.     

555多谐振荡器在模拟声响电路中的应用

555定时器是一种中规模集成电路,它使用灵活、方便,被广泛应用于脉冲的产生、整形、定时和延迟等电路中。文中介绍了555定时器及其逻辑功能,以及由其构成的多谐振荡器的工作原理,通过举例论述了555多谐振荡器在模拟声响电路中的应用,说明在实际生产中,只要将其各个功能加以综合应用,便可得到许多实用电路。     

一种由555定时器实现的双音报警电路

555定时器是一种数模混合的中规模集成电路,它使用灵活、方便,被广泛应用于脉冲的产生、整形变换等电路中。本文介绍了555定时器的组成、功能及由它构成的多谐振荡器的工作原理,论述了一种由555多谐振荡器实现的双音报警电路,说明在实际生产中,只要将555定时器各个功能加以综合应用,便可得到许多实用电路。     

555定时器的典型应用及OrCAD／PSpice仿真

分析了555定时器内部结构及其工作原理,利用OrCAD/PSpice对555定时器构成的单稳态触发器、施密特触发器和多谐振荡器的工作特性进行了仿真,针对仿真过程中多谐振荡器不起振的问题进行了分析,找出了两种振荡电路的有效起振方法,结果表明仿真结果与理论计算值基本相符,对555定时器的综合设计应用具有一定的参考意义.     

一种空气等离子切割电源引弧电路的研究

传统的高频引弧电路存在干扰严重，体积大、效率低等缺点。文章提出一种以NE555多谐振荡器为核心的高频引弧器，给出了该电路的引弧工作原理及参数设计方法，并通过对其输出电流信号和开关信号的检测，实现了DSP对其引弧过程的控制，最后对引弧电路进行仿真与实验，结果表明，引弧电路受干扰大大减小，引弧能力强，安全可靠。     

Design of ultra low power current mode logic gates using magnetic cells

Non-volatile logic is a viable solution to overcome the leakage power issue which has become a major obstacle to CMOS technology scaling. Magnetic tunnel junction (MTJ)-based logic is a promising approach because of the non-volatility, less occupied area, almost zero static power consumption, programmability. This paper presents current mode logic gates using MTJ elements without any intermediate electronic circuitry. This efficient solution reduces the performance overheads of the spintronic logic circuits while simplifying fabrication. Hspice based simulations have been carried out to verify the performance of different logic gates. The simulation results reveal that the SBEG based gates provide less area, power consumption, and energy while also offering less design complexity as compared to mLogic (previously proposed magnetic logic) and CMOS gates.     

基于NCV门库的可逆逻辑门进化设计与优化

提出和实现了一种基于遗传算法的可逆逻辑门的设计方法。其特点是预先求出并存储所需功能的可逆逻辑门的真值表,并对NCV基本门库中的控制V门,控制V+门,控制非门,非门进行编码,通过这些基本门的级联,构成染色体暨可逆逻辑门,在逐代进化中按照既定逻辑功能和优化目标进行适应度评估,再利用遗传换代中的选择,交叉,变异等功能进行遗传操作,进而找到功能和性能均符合预定目标的可逆逻辑门。实验结果证明,此方法的可行性、有效性,与传统手工设计可逆逻辑门相比,其在求解速度和能力方面有显著提高。     

On circuit techniques to improve noise immunity of CMOS dynamic logic

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.     

An integrated injection logic (I/SUP 2/L) macromodel including lateral and current redistribution effects

An integrated logic (I/SUP 2/L) macromodel for computer simulation of logical configurations of I/SUP 2/L gates is presented. The macromodel is synthesized from the familiar Ebers-Moll equivalent circuit which permits compatibility with numerous presently available circuit simulators. Measurement procedures are described for the complete and self-consistent set of electrical parameters required for macromodel definition. A five-stage ring oscillator is computer simulated to demonstrate the application of the macromodel. Lateral current transfer (LCT) between adjacent gates and injector current redistribution (ICR) effects are shown to reduce gate propagation delay times. When both effects are included, the macromodel produces an agreement between computer simulated and experimental results of better than 10 percent. A ring oscillator example illustrates the use of the macromodel to provide physical insight into the layout sensitivity of I/SUP 2/L.     

THE NEW SUPER-HIGH-SPEED DIGITAL CIRCUIT BASED ON LINEAR AND-OR GATES

The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.     

设计和表征一个65nm抗辐射标准单元库

提出了一个基于商用65nm工艺在晶体管级设计抗辐射数字标准单元库的方法。因为当C单元的两个输入是不同的逻辑值时输出会进入高阻模式,并保持输出逻辑电平不变,而当输入端有相同的逻辑值时,C单元的功能就像一个反相器的特性。因此它有把因为辐射粒子引起的单粒子翻转（SEU）效应或单粒子传输（SET）效应所产生的毛刺滤除掉的能力。在这个标准单元库中包含了在晶体管级使用C单元设计了抗辐射的触发器,以便于芯片设计者可以使用这个库来设计具有更高抗辐射能力和减小面积、功耗和延迟的芯片。在最后为了能表征标准单元在硅片上的延迟特性,一个基于环形振荡器的芯片结构用来测量每个单元的延迟,以及验证抗辐射能力。延迟测量结果跟版图后仿真结果偏差在10％以内。     

The IBM Yorktown simulation engine

The IBM Yorktown Simulation Engine (YSE) is a special-purpose, highly parallel programmable machine for the gate-level simulation of logic. A YSE has been constructed at the IBM T. J. Watson Research Center. A full configured YSE could simulate up to two million gates at a speed of over three billion gate simulations per second, it is estimated that a YSE could simulate an IBM 3081 processor, at the gate level, at a rate of 1000 System/370 instructions per second. This paper describes the YSE architecture and software support.     

采用阴影投射法实现的光学并行模糊逻辑

本文提出了一种新的空间编码方法并利用阴影投射系统实现了光学并行模糊逻辑门。本系统可全光学并行实现模糊逻辑中的七种基本逻辑运算,并给出了实验结果。     

Optimization of GaAs MESFET logic gates with subnanosecond propagation delays

This paper describes the optimization of logic gates using GaAs MESFETs. Nonlinear stored charges are evaluated, and propagation delays and power dissipations are computed for logic gates with and without load driver. The performances of these two circuit alternatives are compared, and parameter values are optimized to provide a minimum propagation delay for a given power allocation.