A Novel Four-Mask-Step Low-Temperature Polysilicon Thin-Film Transistor With Self-Aligned Raised Source/Drain (SARSD)

In this letter, a novel structure of polycrystalline-silicon thin-film transistors (TFTs) with self-aligned raised source/drain (SARSD) and a thin channel has been developed and investigated. In the proposed structure, a thick SD and a thin active region could be achieved with only four mask steps, which are less than that in conventional raised SD TFTs. The proposed SARSD TFT has a higher on-state current and a lower off-state leakage current. Moreover, the on/off current ratio of the proposed SARSD TFT is also higher than that of a conventional coplanar TFT     

A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 10⁷ to 1.39 times 10⁷. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.     

Gated-four-probe a-Si:H TFT structure: a new technique to measurethe intrinsic performance of a-Si:H TFT

In this letter, a new technique based on gated-four-probe hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structure is proposed. This new technique allows the determination of the intrinsic performance of a-Si:H TFT without any influence from source/drain series resistances. In this method, two probes within a conventional a-Si:H TFT are used to measure the voltage difference within a channel. By correlating this voltage difference with the drain-source current induced by applied gate bias, the a-Si:H TFT intrinsic performance, such as mobility, threshold voltage, and field-effect conductance activation energy, can be accurately determined without any influence from source/drain series resistances     

A new polysilicon CMOS self-aligned double-gate TFT technology

In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and experimentally demonstrated. The self-alignment between the top- and bottom-gate is realized by a backlight exposure technique. The structure has an ultrathin channel region (300 /spl Aring/) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain field and the full depletion of the ultrathin channel. Moreover, for n-channel devices, the SA-DG TFT has a 4.2 times higher on-current (V/sub gs/=20V) as compared to the conventional single-gate TFT. Whereas for the p-channel devices, the SADG TFT has a 3.6 times higher on-current (V/sub gs/=-20V) compared to the conventional single-gate device.     

Influence of lateral electric field on the anomalous leakagecurrent in polysilicon TFT'S

An unique approach is proposed to investigate the anomalous leakage current in polysilicon thin-film transistors (TFT's). The approach utilizes test structures which have nonuniform film thickness at the drain, source and channel regions, These structures are used to analyze the influence of the lateral electric field on the leakage current. An order of magnitude reduction in leakage current at high drain bias is observed in the thick drain TFT structure compared to the thin drain structure. The improvement on the leakage current is due to the reduction in lateral electric field at the thicker drain. The influence of the lateral electric field on the anomalous leakage current is investigated with the grain boundary trapping effects separated out     

A novel self-aligned bottom gate poly-Si TFT with in-situ LDD

A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is proposed and experimentally demonstrated. The unique feature of the technology is the formation of self-aligned and symmetrical lightly doped source/drain (LDD) structure without any additional photolithographic or implantation steps. Thus, the number of masks used in the technology is the same as that in a conventional top gate TFT technology. Moreover, devices formed by the proposed method have thick source/drain and a thin channel region for providing low source/drain resistance and improved I-V characteristics. P-channel TFT devices are fabricated using a simple low temperature (⩽600°C) process. The fabricated SABG-TFT exhibits symmetrical transfer characteristics when the polarity of source/drain bias is reversed. The effective mobility and on-off current ratio of the devices are about 35 cm²/V-s and 6×10⁶ respectively     

多晶硅超薄沟道薄膜晶体管研制

提出了一种新结构的低温多晶硅薄膜晶体管 ( poly- Si TFT) .该 poly- Si TFT由一超薄的沟道区和厚的源漏区组成 .超薄沟道区可有效降低沟道内陷阱密度 ,而厚源漏区能保证良好的源漏接触和低的寄生电阻 .沟道区和源漏区通过一低掺杂的交叠区相连接 .该交叠区使得在较高偏置时 ,靠近漏端的沟道区电力线能充分发散 ,导致电场峰值显著降低 .模拟结果显示该TFT漏电场峰值仅是常规 TFT的一半 .实验结果表明该 TFT能获得好的电流饱和特性和高的击穿电压 .而且 ,与常规器件相比 ,该 TFT的通态电流增加了两倍 ,而最小关态电流减少了3.5倍 .     

A device model for the amorphous-silicon staggered-electrodethin-film transistor

A model for the amorphous-silicon (a-Si) staggered-electrode thin-film transistor (TFT) that incorporates gate-voltage dependent mobility for channel current and space-charge-limited current effects for the source and drain contacts is discussed. This model is in excellent agreement with TFT data over a wide range of applied voltages and for various channel lengths. For the devices measured, the TFT current depends more sensitively on effective channel mobility than on space-charge-limited current through the a-Si layer, but the latter is responsible for current crowding at low drain voltage. Because of the two-dimensional current flow under the contacts, their equivalent lumped element model exhibits a different power law behaviour than that for one-dimensional current flow in an n⁺-i-n⁺ structure. It also shows that a peak in the differential conductance curve at low drain voltage is a sensitive indicator of current crowding and implies a superlinear equivalent lumped element in series with the intrinsic TFT     

High-performance poly-Si TFTs fabricated by implant-to-silicide technique

High-performance poly-Si thin-film transistors (TFTs) with fully silicided source/drain (FSD) and ultrashort shallow extension (SDE) fabricated by implant-to-silicide (ITS) technique are proposed for the first time. Using the FSD structure, the S/D parasitic resistance can be suppressed effectively. Using the ITS technique, an ultrashort and defect-free SDE can also be formed quickly at about 600/spl deg/C. Therefore, the FSD poly-Si TFTs exhibits better current-voltage characteristics than those of conventional TFTs. It should be noted that the on/off current ratios of FSD poly-Si TFT (W/L=1/4/spl mu/m) is over 3.3/spl times/10/sup 7/, and the field-effective mobility of that device is about 141.6 (cm/sup 2//Vs). Moreover, the superior short-channel characteristics of FSD poly-Si TFTs are also observed. It is therefore believed that the proposed FSD poly-Si TFT is a very promising TFT device.     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

Metal-replaced junction for reducing the junction parasitic resistance of a TFT

Thin-film transistors (TFTs) with metal-replaced junctions (MERJs) have been fabricated and characterized. The junction parasitic resistance of a MERJ TFT is significantly reduced by partially replacing the semiconductor source and drain with a metal. The replacement process was executed at a low temperature of 400/spl deg/C with minimum added process complexity. Compared to a TFT with regular semiconductor source and drain junctions, a MERJ TFT was found to exhibit higher effective values of field-effect mobility and ON-state current.     

A novel self-aligned double-gate TFT technology

In this letter, a novel self-aligned double-gate (SADG) thin-film transistor (TFT) technology is proposed and experimentally demonstrated for the first time. The self-alignment between the top-gate (TG) and bottom-gate (BG) is realized by a noncritical chemical-mechanical polishing (CMP) step. An ultrathin channel and a thick source/drain, that allow better device performance and lower source/drain resistance, are also automatically achieved. N-channel poly-Si TFTs are fabricated with maximum processing temperature below 600°C. Metal induced unilateral crystallization (MIUC) is used for poly-Si grain size enhancement. The fabricated SADG TFT exhibits symmetrical bidirectional transfer characteristics when the polarity of source/drain bias is interchanged. The on-current under double-gate operation is more than two times the sum of that under TG and BG operation     

Kink-free polycrystalline silicon double-gate elevated-channelthin-film transistors

The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented     

A new poly-Si thin-film transistor with poly-Si/a-Si double activelayer

A new poly-Si TFT employing a rather thick poly-Si (400 Å)/a-Si(4000 Å) double active layer is proposed and fabricated in order to improve the stability of poly-Si TFT without sacrificing the on/off current ratio. Due to the thick double layer the on-state drain current of the proposed TFT flows through a broad current path near the drain junction so that the current density in the drain depletion region where large electric field is applied is considerably reduced. Consequently, additional trap state generation attributed to large current flow and large electric field in poly-Si channel decreases and the electrical stability of the proposed device has been considerably improved     

Ultra-thin elevated channel poly-Si TFT technology forfully-integrated AMLCD system on glass

A novel low temperature poly-Si (LTPS) TFT technology called the ultra-thin elevated channel TFT (UT-ECTFT) technology is proposed. The devices fabricated using this technology have an ultra-thin channel region (300 Å) and a thick drain/source region (3000 Å). The ultra-thin channel region is connected to the heavily doped thick drain/source region through a lightly doped overlapped region. The ultra-thin channel region is used to obtain a low grain-boundary trap density in the channel, and the overlapped lightly doped region provides an effective way for electric field spreading at the drain, thereby reducing the electric field there significantly. With the low grain-boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are obtained in the UT-ECTFT. Moreover, this technology provides complementary LTPS TFT's with more than two times increase in on-current and 3.5 times reduction in off-current compared to conventional thick channel LTPS TFT's     

High-Performance Double-Channel Poly-Silicon Thin-Film Transistor With Raised Drain and Reduced Drain Electric Field Structures

In this paper, a high-performance single-gate double-channel polycrystalline-silicon thin-film transistor (DCTFT) is proposed and experimentally demonstrated for the first time. Two thin channels, accompanied with a raised source/drain (S/D) area, an offset structure, a drain field plate, and a field-induced drain region, are used in this device, allowing a lower S/D resistance and a better device performance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability, such as threshold voltage shift and drain on-current degradation under a high gate bias, is also improved by the design of two channels and the reduced drain electric field structures. The lower drain electric field of the DCTFT is also beneficial to scaling down the device for a better performance.      

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the on state, an inversion layer is induced by the subgate as a drain so that the on current is still high and the poly-Si region under the subgate behaves as an offset, reducing the off-state leakage current during the off-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum off-state leakage current of the new TFT is decreased from 1.4/spl times/10/sup -10/ to 1.3/spl times/10/sup -11/ without sacrifice of the on current. In addition, the on-off current ratio is significantly improved.     

A novel gate-overlapped LDD poly-Si thin-film transistor

We fabricate a new polycrystalline silicon thin-film transistor (poly-Si TFT), called a gate-overlapped lightly doped drain (GO-LDD) TFT, which reduces the leakage current without sacrificing the ON current. A new GO-LDD TFT, of which the electrical characteristics are tolerable to the change of LDD doping concentration, can be easily fabricated by employing the buffer oxide without any additional LDD implantation. The change of ON current due to the misalignment of the LDD region may be eliminated. Experimental results show that the leakage current of the proposed TFT's is reduced by two orders of magnitude, compared with that of conventional nonoffset TFT, while the ON current is not decreased. It is observed that the ON/OFF current ratio is not changed significantly with LDD doping concentration and LDD length     

A Novel Blocking Technology for Improving the Short-Channel Effects in Polycrystalline Silicon TFT Devices

An original blocking technology is proposed for improving the short-channel characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs). In particular, two types of modified devices called poly-Si TFT with block oxide and poly-Si on partial insulator (POPI)-TFT are designed for the first time in this field to enhance device performance. The proposed TFT structures can significantly reduce short-channel effects when compared with a thick source/drain (S/D) poly-Si TFT (i.e., the fully depleted TFT). In addition, an ultrathin (UT) S/D structure (UT-TFT) is designed to verify that the block oxide TFT devices do achieve improved performance without needing the thin active layers and ultrashallow junction depth. Also, the POPI-TFT is found to reduce the thermal instability through its natural body-tied scheme.     

A novel offset gated polysilicon thin film transistor without anadditional offset mask

We have proposed a novel offset gated polysilicon TFT fabricated without an offset mask in order to reduce leakage current and suppress the kink effect. The photolithographic process steps of the new TFT device are identical to those of conventional non-offset structure TFT's and an additional mask to fabricate an offset structure is not required in our device. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The novel TFT also exhibits a considerable reduction in the kink effect because a very thin film TFT may be easily fabricated due to the elimination of the contact over-etch problem