CDMA系统序列捕捉中的双截断序贯似然比检测

本文研究DS/CDMA系统中的序列捕捉问题,介绍了一种双截断序贯似然比检测判决(DTSPRT)算法及一种基于状态图的DTSPRT性能分析方法。文中给出了DTSPRT算法各主要参数的计算公式和参考取值范围。理论分析和计算机仿真结果均表明,DTSPRT应用于DS/CDMA系统可节省平均捕捉时间,提高捕捉性能,且实现的复杂度不高。     

认知无线电中基于截断序贯检测的频谱感知技术

序贯检测的检测时间是随实际接收信号采样点的变化而不同的随机变量,在平均意义上,序贯检测有较高的检测速度,但是个别情况下可能需要很长的检测时间,为了避免这种现象的发生,同时提高认知无线电中频谱感知的速度,该文提出了一种截断序贯检测算法。首先分析了截断对传统序贯检测性能的影响,给出了虚警概率和漏检概率的上限,然后基于该性能上限得到了截断序贯检测的检测门限,最后给出了截断序贯检测算法的流程。仿真结果表明,该算法在有限的检测时间内,能够满足系统的性能要求,且其平均检测时间小于传统的能量检测。     

Truncated Sequential Life Tests for a 3-Way Decision Procedure

Eleven sets of test plans are given for testing ``? = ?0' against the alternative ``? = ?1 < ?0' and ``? = ?2 > ?0' where ? is the failure rate. The results are useful for incentive plans and life-cycle costing applications, and are fundamental in the life testing of equipment, whether a consumer or industrial item, during the constant failure-rate period. The theory and equations for the calculations of the tables and plans are developed and discussed and the related references are included.     

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.     

序贯概率比检验用于残差检测的一种改进方法

分析了Wald序贯概率比检验用于故障诊断残差检测时备选假设必须唯一确定所带来的潜在局限性.在残差为正态分布的条件下,针对这种局限性提出了一种改进方法,在残差检测过程不断对备选假设进行修正,并消除了Wald序贯概率比检验产生的检测延时,定性分析认为这种改进方法适合于传感器缓变故障残差检测.仿真结果表明.改进方法相比于Wald序贯概率比方法,能更快速准确地检出缓变故障,具有更高的实时性.     

时序电路的模糊化测试生成算法

文章提出的模糊化的时序电路测试生成算法不明确指定故障点的故障值，它将故障值模糊化，并以符号表示。本算法第一阶段通过计算状态线和原始输出端的故障值来寻找测试矢量，通过计算故障点的正常值来 寻找测试矢量对应的故障类型；第二阶段用故障点的正常值作为约束条件计算故障点的另一个测试矢量。与传统的算法不同，它不需要回退和传播的过程。实验结果表明本算法具有较高的故障覆盖率和较少的测试时间。     

定时截尾试验零故障时的MTBF估计方法

针对产品定时截尾试验中零故障时无法进行平均故障间隔时间(Mean Time Between Failures,MTBF)估计的问题,分析了不同情况下点估计方法选用的注意事项,并通过公式推导得出了零故障时置信下限的计算公式。对置信下限计算公式进一步推导,得到了便于实际应用的简化计算公式。通过在多个可靠性试验中应用该方法进行MTBF估计,结果表明该方法可行有效。     

Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits

We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: (1) fault-list and test-set partitioning, and (2) vector re-ordering. Typically, the first few vectors of a test set detect a large number of faults. The remaining vectors usually constitute a large fraction of the test set, but these vectors are included to detect relatively few hard faults. We show that significant compaction can still be achieved by partitioning faults into hard and easy faults, and compaction is performed only for the hard faults. This significantly reduces the computational cost for static test set compaction without affecting quality of compaction. The second key idea re-orders vectors in a test set by moving sequences that detect hard faults to the beginning of the test set. Fault simulation of the newly concatenated re-ordered test set results in the omission of several vectors so that the compact test set is smaller than the original test set. Experiments on several ISCAS 89 sequential benchmark circuits and large production circuits show that our compaction procedure yields significant test set reductions in low execution times.     

Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption

We show that the test generation problem for all single stuck-at faults in sequential circuits with internally balanced structures can be reduced into the test generation problem for single stuck-at faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper, we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at faults on separable primary inputs.     

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints

The paper proposes a hierarchical untestable stuck-at fault identification method for non-scan synchronous sequential circuits. The method is based on deriving, minimizing and solving test path constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path constraints for a module under test. Then, the constraints are minimized using an SMT solver Z3 and a logic minimization tool ESPRESSO. Finally, a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in sequential circuits. We show by experiments that the method is capable of quickly proving a large number of untestable faults obtaining higher fault efficiency than achievable by a state-of-the-art commercial ATPG. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored.     

概率比序贯试验方案在LED产品中的应用

本文以一个具体试验方案为例介绍概率比序贯试验方案在LED产品中的应用。     

Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits

Automatic test pattern generation (ATPG) remains one of themost complex CAD tasks. Therefore, numerous methods were proposed tospeed up ATPG by using parallelism. In this paper, we focus onparallelizing ATPG for stuck-at faults in sequential circuits bycombining fault and search space parallelism. Fault parallelism isapplied to so-called easy-to-detect faults. The main task of thisapproach is to find a best-suited partitioning of the fault list,based on dependencies between faults. For hard-to-detect faultsleft by fault parallelism, search space partitioning is applied,integrating depth-first and breadth-first search. Since a smalltest set size is mandatory for a cheap test and fault parallelismincreases the number of test patterns, test set compaction is donein a post-processing phase. Results show that our approach is notonly capable of achieving potentially superlinear speedups, but alsoimproves test set quality. The parallel environment we use consistsof a network of 100 workstations connected via ethernet.     

时序系统的状态组区别序列测试方法

介绍了采用单变迁故障模型的时序系统状态组区别序列测试方法,通过选择状态组区别序列优化测试序列长度。这种测试生成方法比时序电路门级测试生成快得多,而且能达到很高的故障覆盖率。     

Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach

Symbolic and genetic techniques are combined in a new approach to sequential circuit test generation that uses circuit decomposition, rather than the algorithmic decomposition used in previous hybrid test generators. Symbolic techniques are used to generate test sequences for the control logic, and genetic algorithms are used to generate sequences for the datapath. The combined sequences provide higher fault coverages than those generated by existing deterministic and GA-based test generators, and execution times are significantly lower in many cases.     

时序电路测试生成新算法研究

为解决同步时序电路的测试难题,提高时序电路测试生成效率,进行了时序电路测试生成算法的研究,将粒子群优化算法应用在时序电路的测试生成中。为验证PSO算法性能,首先将其用于函数优化,能获得较好的优化结果。之后建立自动测试生成离散粒子群速度—位置模型,针对国际标准时序电路的验证结果表明,与同类算法相比,该算法可以获得较高的故障覆盖率和较小的测试矢量集。     

序贯概率比测试法（SPRT）PCM帧同步性能分析

本文分析研究了序贯概率比测试法用于PCM帧同步检测的性能问题,给出了理论分析表达式。     

序贯Bayes概率比检验在雷达可靠性试验中的应用

依据经典概率统计原理设计试验方案进行舰炮雷达靶场可靠性试验,试验统计分析需要较大样本量,实施难度大。利用Bayes序贯概率比检验,可以有效解决这一问题。本文从经典概率统计可靠性检验入手,详细介绍基于Bayes序贯概率比检验理论的可靠性检验原理及方案,并结合某型雷达试验实例进行分析,介绍其在雷达可靠性试验中的应用。     

序贯Bayes概率比检验在雷达可靠性试验中的应用

依据经典概率统计原理设计试验方案进行舰炮雷达靶场可靠性试验，试验统计分析需要较大样本量，实施难度大。利用Bayes序贯概率比检验，可以有效解决这一问题。本文从经典概率统计可靠性检验入手，详细介绍基于Bayes序贯概率比检验理论的可靠性检验原理及方案，并结合某型雷达试验实例进行分析，介绍其在雷达可靠性试验中的应用。     

Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations

The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles, both, data and control parts of the design in a uniform manner is proposed. The method combines deterministic and simulation-based techniques. On the register-transfer level, deterministic path activation is combined with simulation based-techniques used for constraints solving. The gate-level local test patterns for components are randomly generated driven by high-level constraints and partial path activation solutions. Experiments show that high fault coverages for circuits with complex sequential structures can be achieved in a very short time by using this approach.