Substrate noise coupling through planar spiral inductor

While precious studies on substrate coupling focused mostly on noise induced through drain-bulk capacitance, substrate coupling from planar spiral inductors at radiofrequency (RF) via the oxide capacitance has not been reported. This paper presents the experimental and simulation results of substrate noise induced through planar inductors. Experimental and simulation results reveal that isolation between inductor and noise source is less than -30 dB at 1 GHz. Separation by distance reduces coupling by less than 2 dB in most practical cases. Practical examples reveal an obstacle in integrating RF tuned-gain amplifier with sensitive RF receiver circuits on the same die. Simulation results indicate that hollow inductors have advantages not only in having a higher self-resonant frequency, but also in reducing substrate noise as compared to conventional inductors. The effectiveness of using a broken guard ring in reducing inductor induced substrate noise is also examined     

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate

Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations at the circuit level of the substrate noise coupling in large systems-on-chip (SoCs) do not provide the necessary understanding in the problem. Analysis at a higher level of abstraction gives much more insight in the coupling mechanisms. This paper presents a physical model to estimate and understand the substrate noise generation by a digital modem, the propagation of this noise and the resulting performance degradation of LC tank VCOs. The proposed linearized model is fast to derive and to evaluate, while remaining accurate. It is validated with measurements on two test structures: a reference design and a design with a$hboxp^+ $/n-well (digital) guard ring. Both structures contain a functional 40k gate digital modem and a 0.18$muhbox m$3.5 GHz CMOS LC-VCO on a lightly-doped substrate. In both cases, the model accurately predicts the level of the spurious components appearing at the VCO output due to the digital switching activity. The error remains smaller than 3 dB. Finally, we demonstrate how the proposed model enables a systematic and controlled isolation strategy to suppress substrate noise coupling problems. As an example, the model is used to determine suitable dimensions for a digital guard ring.     

Experimental results and modeling techniques for substrate noise inmixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed     

3-D Integration of 10-GHz Filter and CMOS Receiver Front-End

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mum CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.     

Impact of Substrate Digital Noise Coupling on the High-Frequency Noise Performance of RF MOSFETs

The impact of digital noise coupling through the substrate on RF MOSFETs was investigated in terms of the noise figure (NF) of the device up to 26.5 GHz. Previous works on the substrate digital noise coupling have treated the effect mostly in terms of the electrical isolation between ports, rather than actual devices, which does not provide direct information on the degradation of actual device performance parameters from such coupling. In this work, an actual NMOSFET was employed for test and the effect was described in terms of NF, a practical device performance parameter. The results show that NF is significantly degraded as the device enters the weak inversion state and/or $V_{rm ds}$ becomes smaller, suggesting a trade-off between low power operation and immunity against the substrate noise coupling. Also, it is experimentally verified that devices with a dual guard ring showed much smaller NF than those with a single guard ring.      

An experimental study on substrate coupling in bipolar/BiCMOS technologies

The parasitic influence of the substrate can lead to a significant performance degradation of advanced high-speed and RF circuits. Hence, a careful circuit layout is necessary, and shielding measures such as guard rings must usually be applied. However, this might not be sufficient for high-performance circuits. Moreover, such measures often lead to an increased chip size. Therefore, not only the layout but also the technology itself should be optimized to suppress substrate coupling as much as possible. In this work, different technology-related options such as high-resistivity and SOI substrates, transistor isolation techniques, and shielding methods are investigated. Their influence on substrate coupling is determined up to 50 GHz by measurements of special test structures. The observed behavior is thoroughly explained so that guidelines for technology development and circuit design can be derived. This paper focuses primarily on RF and high-speed ICs fabricated in advanced bipolar or BiCMOS technologies using p/sup -/ substrates, although the results apply also to (RF-)CMOS circuits with such substrate materials.     

Crosstalk between finite ground coplanar waveguides over polyimide layers for 3-D MMICs on Si substrates

Finite-ground coplanar (FGC) waveguide lines on top of polyimide layers are frequently used to construct three-dimensional Si-SiGe monolithic microwave/millimeter-wave integrated circuits on silicon substrates. Requirements for high-density, low-cost, and compact RF front ends on silicon can lead, however, to high crosstalk between FGC lines and overall circuit performance degradation. This paper presents theoretical and experimental results and associated design guidelines for FGC line coupling on both highand low-resistivity silicon wafers with a polyimide overlay. It is shown that a gap as small as 6 /spl mu/m between two adjacent FGC lines can reduce crosstalk by at least 10 dB, that the nature of the coupling mechanism is not the same as with microstrip lines on polyimide layers, and that the coupling is not dependent on the Si resistivity. With careful layout design, isolation values of better than -30 dB can be achieved up to very high frequencies (50 GHz).     

A micromachining technology for integrating low-loss GHz RF passives on non-high-resistivity low-cost silicon MCM substrate

A micromachining technology for integrating high-performance radio-frequency (RF) passives on CMOS-grade low-cost silicon substrates is developed. The technology can form a thick solid-state dielectric isolation layer on silicon substrate through high-aspect-ratio trench etch and refill. On the non-high-resistivity but low-loss substrate, two metal layers with an inter-metal dielectric layer are formed for integrating embedded RF components and passive circuits. Using the technology, two types of integrated RF filters are fabricated that are band-pass filter and image-reject filter. The band-pass filter shows measured minimum insertion loss of 3.8 dB and return loss better than 15 dB, while the image-reject filter exhibits steeper band selection and achieves better than −30 dB image rejection. A 50 Ω co-planar waveguide (CPW) on the substrate is also demonstrated, showing low loss and low dispersion over the measured frequency range up to 40 GHz. The developed technology proves a viable solution to implementing silicon-based multi-chip modules (MCM) substrates for RF system-in-package (RF-SiP).     

The importance of distributed grounding in combination with porous Si trenches for the reduction of RF crosstalk through p/sup -/ Si substrate

Locally incorporated porous Si (PS) trenches are used for radio frequency (RF) crosstalk isolation through p/sup -/ Si substrates. PS trenches provide large dielectric separation (large impedance) between the noise producing and the noise sensitive circuits without prohibitively high stress from a thermal expansion coefficient mismatch between bulk Si and the common dielectrics, e.g. SiO/sub 2/ and Si/sub 3/N/sub 4/. A variety of commonly used RF isolation structures are fabricated and compared. The best isolation structure for the p/sup $/substrates is shown to be the one with p/sup +/ grounding stripes in addition to a PS trench. Crosstalk between Al pads with 800 /spl mu/m separation is reduced to the level comparable to that through air. It is shown that contrary to our previous result using PS trenches in p/sup +/ substrates, p/sup +/ grounding stripes or PS trenches alone is quite ineffective. Superior RF isolation is achieved only when the two approaches are used in conjunction with one another. The combined approach results in additional crosstalk reduction of 21 dB at 2 GHz and 11 dB at 20 GHz.     

Monolithic above-IC resonator technology for integrated architectures in mobile and wireless communication

This paper demonstrates the feasibility of an above-IC bulk acoustic wave technology for wireless applications. A double-lattice bulk acoustic wave (BAW) filter with balanced input and output has been designed and integrated as a post-process directly above 0.25 /spl mu/m BiCMOS wafers comprising RF circuits. This filter, featuring moderate insertion loss of -3dB and extreme out-of-band rejection (>-50 dB) is used in a simplified RF front-end receiver for the WCDMA standard, as well as in a new type of filtering LNA comprising two broadband amplifiers and one BAW filter.     

SOI数模混合集成电路的串扰特性分析

采用二维TMA Medici模拟软件对SOI结构的串扰特性进行了分析.模拟发现随着频率的增加,SOI的埋氧化物对串扰噪声几乎不起隔离作用,同时,连接SOI结构的背衬底可以在很大程度上减小串扰的影响.还对减少串扰的沟槽隔离工艺、保护环及差分结构的有效性进行了比较分析,对一些外部寄生参数对串扰的影响也进行了研究.并给出了SOI结构厚膜和薄膜结构体掺杂浓度对噪声耦合的影响,所得到的结果对设计低噪声耦合的SOI数模混合集成电路具有指导性的作用.     

Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking

This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise.     

Trenched‐Sinker LDMOSFET (TS‐LDMOS) Structure for 2 GHz Power Amplifiers

This paper proposes a new LDMOSFET structure with a trenched sinker for high‐power RF amplifiers. Using a low‐temperature, deep‐trench technology, we succeeded in drastically shrinking the sinker area to one‐third the size of the conventional diffusion‐type structure. The RF performance of the proposed device with a channel width of 5 mm showed a small signal gain of 16.5 dB and a maximum peak power of 32 dBm with a power‐added efficiency of 25% at 2 GHz. Furthermore, the trench sinker, which was applied to the guard ring to suppress coupling between inductors, showed an excellent blocking performance below ?40 dB at a frequency of up to 20 GHz. These results confirm that the proposed trenched sinker should be an effective technology both as a compact sinker for RF power devices and as a guard ring against coupling.     

High-isolation photonic microwave mixer/link for wideband signal processing and transmission

We have proposed, analyzed, and demonstrated a high-isolation photonic microwave mixer using an integrated, dual-stage balanced-bridge Mach-Zehnder modulator. The proposed balanced photonic microwave mixer provides not only high isolation between radio frequency (RF) signal and local oscillator (LO) ports, but also excellent isolation between intermediate frequency (IF) and RF/LO ports without any filters. In this paper, the structure, principle, and operation settings are discussed in detail. Experimental results showed >60 dB electrical isolation between RF and LO ports and >50 dB isolation between IF and RF/LO ports in a demonstrative photonic microwave mixer. This device can extend the bandwidth of a modulator and have wide applications in RF photonic links where RF signal conversion and processing are required.     

High Performance RF Passive Integration on a Si Smart Substrate for Wireless Applications

To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6“ Si wafer with a 25 μm thick SiO₂ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 Ω coplanar transmission line (W=50 μm, G=20 μm). Using benzo cyclo butene (BCB) interlayers and a 10 μm Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30‐120, depending on geometrical parameters and inductance values of 0.35‐35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high‐speed wireless LAN applications. The chip sizes of the wafer‐level‐packaged RF IPDs and wire‐bondable RF IPDs were 1.0‐1.5 mm² and 0.8‐1.0 mm², respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand‐held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.     

V-band Low-noise Integrated Circuit Receiver

A compact low-noise V-band integrated circuit receiver has been developed for space communication systems, The receiver accepts an RF input of 60-63 GHz and generates an IF output of 3-6 GHz. A Gunn oscillator at 57 GHz is phaselocked to a low-frequency reference source to achieve high stability and low FM noise. The receiver has an overall single sideband noise figure of less than 10.5 dB and an RF to IF gain of 40 dB over a 3-GHz RF bandwidth. All RF circuits are fabricated in integrated circuits on a Duroid substrate.     

The fabrication of thin-film bulk acoustic wave resonatorsemploying a ZnO/Si composite diaphragm structure using porous siliconlayer etching

Thin-film bulk acoustic wave resonators (FBARs) are used in monolithic microwave integrated circuits (MMICs) for semiconductor devices. FBARs are more attractive than surface acoustic wave resonators since they have the advantages of small size, low cost, and mass-production ability. In this letter, an FBAR with an air gap is fabricated by a surface micromachining technique which utilizes porous silicon layer (PSL) etching. This FBAR has a forward reflection coefficient of -18.912 dB when the thickness of the ZnO thin film measures 1 μm. The FBAR is composed of a piezoelectric zinc oxide (ZnO) thin film and top and bottom electrode thin films of Au(1000 Å)/Ni-Cr(50 Å). The ZnO thin film is deposited by RF magnetron sputtering. This fabrication process is compatible with conventional IC processes, thereby enabling the development of monolithic-integrated FBAR's on Si or GaAs substrates     

Methods for measurement and simulation of weak substrate couplingin high-speed bipolar ICs

On-wafer measurements of very weak substrate coupling in high-speed integrated circuits (ICs) at high frequencies suffer from the direct crosstalk between the input and output RF probes. Two alternative methods to reduce this effect are presented and compared. The first one is based on an advanced deembedding method that eliminates the crosstalk between the RF probes after measurement. The second method utilizes an on-chip broad-band amplifier between the input probe and the substrate test structure. Thus, for a given signal amplitude at the output probe, the amplitude of the input signal can be reduced, resulting in less distortion of the output signal by the crosstalk via the probes. Both methods are compared and verified by measurements up to about 20 GHz even at substrate coupling impedances as high as 0.5 MΩ (corresponding to -80 dB in a 50-Ω system). For this, several substrate test structures (some with the 20-GHz on-chip amplifier) have been designed and fabricated in an SiGe bipolar production technology with 20-Ωcm substrate resistivity. The measurement results agree well with simulation results using our substrate simulator SUSI. As a consequence, the inflexible, expensive, and time-consuming way to determine substrate coupling experimentally is no longer required in future IC designs-not even at very weak coupling and high frequencies. In this work, however, the proposed measuring methods had to be applied to verify the suitability of substrate simulation (with SUSI) under extreme conditions     

GaAs monolithic Lange and Wilkinson couplers

An important part of monolithic microwave integrated circuits are the passive distributed circuit elements which divide and combine RF signals. This paper describes the design and performance of a monolithic GaAs X-band three-port Wilkinson coupler [1] and a monolithic GaAs X-band four-port interdigitated Lange coupler [2], [3]. These couplers are useful both as power dividers and power combiners. In the Wilkinson, the input power is split equally between the output ports with zero differential phase shift. For the Lange, there is a phase difference of 90° between the outputs. All ports are well matched and the output ports are highly isolated. The transmission mode chosen for these couplers is microstrip on semi-insulating GaAs with conductor-to-ground plane spacing of 0.1 mm. This low-loss, high permittivity medium is compatible with the present monolithic GaAs FET technology which thus allows combining more complicated monolithic microwave integrated circuits on a single chip. The fabrication process takes advantage of the technology developed for proeessfng GaAs FET's. For example, connecting the coupling conductors for the Lange coupler requires RF crossovers. To minimize crossover capacitance, an air-bridge interconnection technique is used. Calculated coupling, isolation, and VSWR data for the Wilkinson and Lange couplers are compared with actual measured performance showing good agreement with expected results. Measured loss, minus fixture contributions, shows 0.25 dB for the Wilkinson and 0.75 dB for the Lange.     

A wide-band T/R switch using enhanced compact Waffle MOSFETs

A wide-band complementary metal oxide semiconductor (CMOS)transmit/receive (T/R) switch using enhanced compact waffle metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. The compact waffle layout configuration saves much active area to give a low on-resistance. Furthermore,the low drain-to-substrate capacitance (CDB) in waffle MOSFETs can help reduce high frequency substrate coupling and substrate loss for CMOS radio frequency (RF)/microwave integrated circuits (ICs). A 2-dB higher maximum stable gain/maximum available gain (MSG/MAG)and a 2-GHz higher f/sub max/ are obtained compared with those of conventional multifinger MOSFETs. The CMOST/R switch implemented in a standard 0.35-/spl mu/m CMOS technology gives a low insertion loss of 1.7dB,high isolation of more than 40dB, larger than 15-dB return loss, 7-dBm P/sub 1 dB/ and 13-dBm input IP3 at 900MHz with a 3-V supply voltage. The switch maintains a wide-band performance up to 2.4GHz with only a slight deterioration.