BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed     

A 17-ns 4-Mb CMOS DRAM

A 17-ns nonaddress-multiplexed 4-Mb dynamic RAM (DRAM) fabricated with a pure CMOS process is described. The speed limitations of the conventional DRAM sensing technique are discussed, and the advantages of using the direct bit-line sensing technique are explained. A direct bit-line sensing technique with a two-stage amplifier is described. One readout amplifier is composed of a two-stage current-mirror amplifier and a selected readout amplifier is activated by a column decoder output before the selected word line rises. The amplifier then detects a small bit-line signal appearing on a bit-line pair immediately after the word-line rise. This two-stage amplification scheme is essential to improving access time, especially in the case of a CMOS process. The high sensitivity of the readout amplifier is discussed, and the electrical features and characteristics of the fabricated DRAM are reported     

New three-dimensional memory array architecture for futureultrahigh-density DRAM

In this paper, a three-dimensional (3-D) memory array architecture is proposed. This new architecture is realized by stacking several cells in series vertically on each cell located in a two-dimensional array matrix. Therefore, this memory array architecture has a conventional horizontal row and column address and new vertical row address. The total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM when one bit-line has 1-Kbit cells and the same design rules are used. Moreover, an array area of 1-Mbit DRAM using the proposed architecture is reduced to 11.5% of normal DRAM using the same design rules. This proposed architecture's DRAM can realize small bit-line capacitance and small array area simultaneously. Therefore, this proposed 3-D memory array architecture is suitable for future ultrahigh-density DRAM     

High cell-efficiency synchronous MRAM adopting unified bit-line cache

Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.     

Decoded-source sense amplifier for high-density DRAMs

The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a V_cc of 4 V at 85°C     

A 4-Mbit DRAM with 16-bit concurrent ECC

A 256 K-word×16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8-μm CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 μm² with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC     

An experimental DRAM with a NAND-structured cell

An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 μm², using 0.4-μm CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm², which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved     

A divided/shared bit-line sensing scheme for ULSI DRAM cores

A new dynamic RAM (DRAM) signal sensing principle, a divided/shared bit-line (DSB) sensing scheme, is proposed. This sensing scheme provides folded bit-line sensing operation in a crosspoint-type memory cell array. The DSB scheme offers a high-density DRAM memory core with the common-mode array noise eliminated. A bit-line architecture based on this new sensing principle and its operation are demonstrated. A divided/pausing bit-line sensing (DIPS) scheme, which is an application of this DSB principle to the conventional folded bit-line type of memory cell arrangement, is also proposed. The DIPS architecture achieves complete pausing states for alternate bit lines throughout the active period. These alternate pausing bit lines shield the inter-bit-line coupling noise between active bit lines. Here the inter-bit-line coupling noise is eliminated by a slight architectural change to the conventional folded bit-line memory cell array. These new memory core design alternatives provide high-density DRAM memory cores suitable for the 64-Mb level and beyond. with the memory array noise reduced significantly     

A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using aNAND flash memory technology

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-μm triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm², and the effective cell size including the overhead of string select transistors is 2.0 μm²     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed     

A 4-Mbit DRAM with half-internal-voltage bit-line precharge

A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.     

Twisted bit-line architectures for multi-megabit DRAMs

As the memory cell array of DRAM has been scaled down, inter-bit-line coupling noise has emerged as a serious problem. The signal loss due to this noise is estimated at about 40% of the signal amplitude in a polycide-bit-line 16-Mb DRAM with a technologically attainable scaling scheme. Twisted bit-line architectures to reduce or eliminate the noise are proposed and demonstrated by the soft-error rate improvement of a 1-Mb DRAM. The effective critical charge is improved by 35%, which is attributed not only to the improvement of the signal amplitude but also to the elimination of large coupling noise during the sensing operation. The impact of these twisted bit-line architectures from a scaling viewpoint is also examined, and they are shown to be promising candidates for overcoming the scaling problems of DRAMs     

A low-noise folded bit-line sensing architecture for multigigabitDRAM with ultrahigh-density 6F2 cell [CMOS design]

The 6F² cell is widely known for its small area, but its sensing is unstable due to the large array noise. A new low-noise sensing scheme for a 6F² DRAM cell is proposed, employing two noise reduction methods: the divided sense and combined restore scheme and the bit-line noise absorbing scheme. They can reduce word-line to bit-line as well as bit-line to bit-line coupling noises. The bit-line noise is reduced to 85% of that of a conventional scheme with only 0.05% area overhead, which is negligible compared to the area saving by using a 6F² cell. The total chip area and the sensing time can he reduced to 85 and 87%, respectively, compared to conventional DRAM. A 2 kbit DRAM test chip with a 6F² cell Is fabricated using 256 M DRAM technology, and its stable operations are confirmed     

A 33-ns 64-Mb DRAM

A 64-Mb CMOS dynamic RAM (DRAM) measuring 176.4 mm² has been fabricated using a 0.4-μm N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. The asymmetrical stacked-trench capacitor (AST) cells, 0.9 μm×1.7 μm each, are laid out in a PMOS centered interdigitated twisted bit-line (PCITBL) scheme that achieves both low noise and high packing density. Three circuit techniques were developed to meet high-speed requirements. Using the preboosted word-line drive-line technique, a bypassed sense-amplifier drive-line scheme, and a quasi-static data transfer technique, a typical RAS access time of 33 ns and a typical column address access time of 15 ns have been achieved     

Cell-plate-line/bit-line complementary sensing (CBCS) architecturefor ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced     

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-μm L_eff CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm×6.38-mm chip, organized as either 512 K word×8 b or 1 M word×4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V_cc and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V_cc to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time     

A 4-Mbit DRAM with trench-transistor cell

An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.     

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.     

A high-speed sensing scheme for 1T dynamic RAMs utilizing theclamped bit-line sense amplifier

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power     

A 1-Gb DRAM for file applications

A time-shared offset-canceling sensing scheme, a defective word-line Hi-Z standby scheme, and a flexible multimacro architecture have been developed for 1-Gb DRAM. These circuit technologies have been applied to a 1-Gb DRAM for file applications employing 0.25 μm CMOS process technology, a diagonal bit-line cell, and a two-stage pipeline circuit technique. In this DRAM, a 30% chip size reduction and a 400-MB/s data transfer rate have been achieved. A 100% improvement in yield has been estimated by Monte-Carlo simulation. The 1-Gb DRAM die size is 936 mm². The cell size is 0.54 μm². The operating current is 58 mA at 2 V and 100 MHz