基于FPGA的乘法器实现结构分析与仿真

现场可编程门阵列(FPGA)的快速发展为数字信号处理(DSP)系统设计提供了一种新的解决方案，而乘法运算是DSP领域内的一种基本运算，应用极为广泛，对乘法运算基于FPGA的实现结构进行研究具有重要意义。本文分析乘法运算的特点，给出了几种适应FPGA实现的乘法器结构。并在Xilinx公司的ISE 4．1i软件环境下，采用VHDL和VIRELOG硬件描述语言进行了设计实现并对其性能进行了比较分析。     

Evolutionary circuit design for fast FPGA-based classification of network application protocols

The evolutionary design can produce fast and efficient implementations of digital circuits. It is shown in this paper how evolved circuits, optimized for the latency and area, can increase the throughput of a manually designed classifier of application protocols. The classifier is intended for high speed networks operating at 100 Gbps. Because a very low latency is the main design constraint, the classifier is constructed as a combinational circuit in a field programmable gate array (FPGA). The classification is performed using the first packet carrying the application payload. The improvements in latency (and area) obtained by Cartesian genetic programming are validated using a professional FPGA design tool. The quality of classification is evaluated by means of real network data. All results are compared with commonly used classifiers based on regular expressions describing application protocols.     

基于FPGA的图像预处理快速算法及仿真

工程实践中,可编程逻辑器件已经越来越多的受到重视和应用.文中以DSP处理大量数据时,实时性难以达到要求入手,介绍了应用可编程逻辑器件FPGA提高程序效率、实现快速运算的一种方法,并设计了一个利用中值滤波进行图像预处理的系统,之后进行了仿真和实验验证.文章最后得到结论,采用FPGA通过用硬件逻辑来实现运算量大但相对比较简单的算法,效率要大大高于软件的多次循环,若在系统中采用DSP和FPGA合作处理数据,则可以各自发挥长处,实现快速算法.     

FPGA-based methodology for depth-of-field extension in a single image

Computer vision applications rely upon high resolution images with extended depth of field (DoF). Most approaches contain arrays of lenses and computing intensive algorithms that must be calibrated every time, to reach in-focus images; however, by changing directly the system focal length, resolution and information are lost. Traditional methods consist in taking a great number of images varying the optical system pupil aperture, whereas, the post processing system demands a great amount of computational resources with long processing time and high implementation cost. In this work a novel methodology for DoF extension that applies a complex-amplitude mask during a single image pre-processing taken at full pupil aperture, and a Wiener filter for the image recovery without focalization errors, during post-processing, is introduced. An FPGA-based implementation shows the feasibility of the proposed methodology for real-time DoF extension. Obtained results demonstrate qualitatively and quantitatively the effectiveness of the proposed FPGA-based method, which offers a reconfigurable solution for online DoF extension on a single image, in real time.     

An FPGA-based architecture for a local tone-mapping operator

This paper presents an FPGA-based architecture for local tone mapping of gray scale high dynamic range images. The architecture is described in VHDL and has been synthesized using Altera Quartus tools. It achieves an operating frequency consistent with a video rate of 60 frames per second for a frame of 1,024 × 768 pixels. The proposed architecture is a modification of the nine-scale Reinhard operator. Approximations to the original Reinhard operator ensure that the operator is amenable to implementation in hardware. A peak signal-to-noise ratio study shows that our fixed-point hardware approximation produces results similar to a floating-point original.

基于DSP+FPGA的LFMCW雷达测距信号处理系统设计

为解决计算量大的高精度线性调频连续波(LFMCW)雷达测距信号处理算法难以在线验证的问题,提出一种基于数字信号处理器(DSP)和现场可编程门阵列(FPGA)双核架构的雷达测距信号处理系统方案,并完成了软硬件设计和测距算法嵌入.设计方案以DSP为信号处理核心,FPGA为外围设备控制核心.采用C语言实现了基于相位匹配法的LFMCW雷达测距算法在DSP中的嵌入,采用VHDL语言实现FPGA功能模块.在线测距实验结果表明:各功能模块工作正常,基于相位匹配法的测距算法精度高.     

一种基于FPGA的可配置SPI Master接口设计实现

介绍一种基于FPGA的SPI Master Interface设计。依据SPI同步串行接口的通信协议,设计一个可配置的、高度灵活的SPI Master模块,以满足正常、异常及强度测试要求。利用Verilog语言实现SPI接口的设计原理和编程思想。     

Design and implementation of a realtime co-processor for denoising Fiber Optic Gyroscope signal

The amount of noise present in the Fiber Optic Gyroscope (FOG) signal limits its applications and has a negative impact on navigation system. Existing algorithms such as Discrete Wavelet Transform (DWT), Kalman Filter (KF) denoise the FOG signal under static environment, however denoising fails in dynamic environment. Therefore in this paper an Adaptive Moving Average Dual Mode Kalman Filter (AMADMKF) is developed for denoising the FOG signal under both the static and dynamic environments. Performance of the proposed algorithm is compared with DWT and KF techniques. Further, a hardware Intellectual Property (IP) of the algorithm is developed for System on Chip (SoC) implementation using Xilinx Virtex-5 Field Programmable Gate Array (Virtex-5FX70T-1136). The developed IP is interfaced as a Co-processor/ Auxiliary Processing Unit (APU) with the PowerPC (PPC440) embedded processor of the FPGA. It is proved that the proposed system is an efficient solution for denoising the FOG signal in real-time environment. Hardware acceleration of developed Co-processor is 65× with respect to its equivalent software implementation of AMADMKF algorithm in the PPC440 embedded processor.     

基于FPGA的高速高质量图像旋转

为了进行高质量、高速的图像旋转变换 ,通过对传统图像旋转矩阵的分解 ,将图像在二维空间中的旋转运算分解成为三次一维空间内的平移运算 ,从而将用于图像旋转运算的二维插值运算简化为在一维空间中进行的一维插值运算。为了保证图像旋转后的质量 ,采用 3阶 B-样条对每次平移后像素点的灰度值进行插值运算 ,并提出了一种基于 IIR和 FIR数字滤波器的 3阶 B-样条插值法的高速实现方案 ;最后针对 2 5 6灰度级 ,2 5 6× 2 5 6像素的图像设计出一种基于 FPGA的高速、高质量的硬件图像旋转及显示系统     

基于DSP的高速串行数据录放接口设计和实现

介绍了一种用于声纳设备中的高速串行数据记录和回放接口的设计方案。该方案用于实现阵列数字信号处理机与数据记录设备间的连接。文中描述了利用ADI公司SHARC处理器的串行口实现高速数据记录和回放的硬件设计原理,给出了串行编解码方案和软件设计流程。     

基于电感式位移传感器的调焦机构设计

调焦机构是大型光电跟踪设备和变焦距镜头的重要组成部分,调焦精度直接影响整个跟踪控制系统的性能.目前调焦机构大多采用光栅尺作为位移的采集和反馈单元来实现系统的闭环控制,其主要缺陷是体积大、温度适应性差,不能满足对温度要求高的工作环境.设计了一种由电感式直线位移传感器、DSP & FPGA调焦控制板卡、步进电机以及电动平移台组成的宽温调焦机构.详细介绍了系统整体架构、各个单元的硬件实现以及软件操作流程,系统性能参数分析和调焦实验结果表明设计能够满足要求.     

A reconfigurable computing framework for multi-scale cellular image processing

Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. These architectures are a good match for many image and video processing applications and can be substantially accelerated with Reconfigurable Computers. We present a flexible software/hardware framework for design, implementation and automatic synthesis of cellular image processing algorithms. The system provides an extremely flexible set of parallel, pipelined and time-multiplexed components which can be tailored through reconfigurable hardware for particular applications. The most novel aspects of our framework include a highly pipelined architecture for multi-scale cellular image processing as well as support for several different pattern recognition applications. In this paper, we will describe the system in detail and present our performance assessments. The system achieved speed-up of at least 100× for computationally expensive sub-problems and 10× for end-to-end applications compared to software implementations.     

基于DSP和FPGA的被动声探测实时采集系统设计

为了给被动声探测技术研究提供实验验证平台,设计了一种可以进行实时数据采集和处理的系统方案.整个系统以数字信号处理器(DSP)和现场可编程门阵列(FPGA)为基本架构,由FPGA控制模数转换器(ADC)采集数据,通过USB 2.0电路将数据传送给个人计算机(PC),用于初期的离线验证;FPGA将采集到的数据通过外部存储器接口(EMIF)传递给DSP,用于实时处理.实验证明:系统实现了被动声探测中的实时数据采集、离线数据存储.数据采集与数据处理分别由不同处理器执行,提高了系统的响应速度与处理性能,能够满足探测系统的实时性要求.     

Development and applications of an interactive digital filter design program

We have implemented an interactive digital filter design program in the HP 1000 computer at the Department of Electrical Engineering of the University of Washington. This program allows users to design different types of filters interactively with both amplitude and phase responses displayed on graphic devices. The performance of each designed filter can be evaluated conveniently before the best one is chosen and implemented for any particular application. This program can design recursive filters, e.g. Butterworth, Chebyshev and elliptic, or nonrecursive filters with one out of six different windows, i.e. rectangular, triangular, Hann, Hamming, Blackman and Kaiser. The main outputs from this program are coefficients of a transfer function of an analog filter, a digital filter, or both. Therefore, the design of both analog and digital filters is facilitated by using this program. The program is very simple to use and does not require background in analog or digital filter principles in order to run it. The program is written in standard FORTRAN and is about 30 kbytes in size excluding the graphics display routines. Since it uses standard FORTRAN, it can be easily transported to minicomputer and microcomputer systems that have a FORTRAN compiler and minimal graphics capabilities. This program is available for distribution to interested institutions and laboratories.     

A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding

This report describes the design of a modular, massive-parallel, neural-network (NN)-based vector quantizer for real-time video coding. The NN is a self-organizing map (SOM) that works only in the training phase for codebook generation, only at the recall phase for real-time image coding, or in both phases for adaptive applications. The neural net can be learned using batch or adaptive training and is controlled by an inside circuit, finite-state machine-based hard controller. The SOM is described in VHDL and implemented on electrically (FPGA) and mask (standard-cell) programmable devices.     

基于高性能DSP的串行通信实现技术研究

高效的数据通信是实现微型导航计算机系统的关键技术。在基于TMS320C67XX系列DSP芯片实现高性能微导航计算机系统中,采用外扩SC28L198收发器实现异步串行通信,并从系统扩展方案、硬件设计、软件开发等方面全面研究了DSP微型导航计算机串行通信接口。系统测试结果表明,本文设计的软硬件模块,数据通信稳定、可靠,达到了高实时性、强扩展性和可控性的要求。     

基于单片机及FPGA的电力载波通信异常信号监测系统设计

为了保证电力载波通信网络的运行安全,以单片机及FPGA为硬件支持,设计基于单片机及FPGA的电力载波通信异常信号监测系统。根据电力载波通信网络的异常原因,设置异常信号特征作为判据。在建立的电力载波通信网络模型下,利用装设的信号采集设备、单片机以及FPGA元件,采集并处理电力载波通信信号。通过实时通信信号的特征提取与匹配,判定当前信号的异常状态,计算得出通信异常信号量和信号异常类型,最终以可视化的形式输出电力载波通信异常信号的监测结果。通过系统测试得出结论：与传统通信异常信号监测系统对比,优化设计系统的通信异常信号量的监测误差降低了1.37dBm,且通信异常信号类型的误检率得到明显降低。     

BOAR: an advanced HW/SW coemulation environment for DSP system development

The BOAR emulation system is targeted to hardware/software (HW/SW) codevelopment of advanced embedded DSP and telecom systems. The challenge of the BOAR system is efficient customization of programmable hardware, and dedicated partitioning routine to target applications and structures, which allows quite high overall system performance. The system allows multiple configurations for communication between processors and field programmable gate arrays (FPGAs) making the BOAR system an efficient tool for real-time HW/SW coverification. The reprogrammable hardware of the emulation tool is based on four Xilinx 4000-series devices, two Texas TMS320C50 signal processors and one Motorola MC68302 microcontroller. With current devices the BOAR hardware provides approximately 40–70 kgates of logic capacity in DSP applications. The emulation capacity can be expanded by connecting several similar boards in chain. The system has also a versatile internal reprogrammable test environment for test bench development, performance evaluations and design debugging. The logic development environment is based on the Synopsys synthesis tools and an automatic design management software, which performs resource mapping and performance-driven design partitioning between FPGAs. The emulation hardware is currently connected to logic and software development environments via an RS-232C bus. The BOAR emulation system has been found a very efficient platform for real-life prototyping of different types of DSP algorithms and systems, and validating correct functionality of a VHDL macro library.     

用于海洋地震勘探的数字包设计与实现

提出了一种高精度、高性能的用于海洋地震勘探的拖缆数字包,并给出其设计与实现.每个数字包含有16个数据采集通道,每个通道都可以直接连接水听器,而水听器产生的模拟信号被由FPGA控制的24-bit高精度Δ-∑ADC实时采集.同时,基于串行并发总线结构,设计和实现了系统的实时控制和远距离数据传输与同步.测试结果表明:该拖缆数字包满足海洋地震勘探的要求.