0.18 μm 3.1-10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7± 17.4 ps group-delay

A3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only plusmn17.4 ps across the whole band) using standard 0.18 mum CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S₁₁) of -9.7 to -19.9 dB, output return loss (S22) of-8.4 to -22.5 dB, flat forward gain (S21) 11.4 plusmn0.4 dB, reverse isolation (S12) of -40 to -48 dB, and noise figure of 4.12-5.16 dB over the 3.1-10.6 GHz band of interest. A good 1 dB compression point (Pi dB) of -7.86 dBm and an input third-order intermodulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681 x 657 mum excluding the test pads.     

0.18 μm 21-27 GHz CMOS UWB LNA with 9.3 ± 1.3 dB gain and 103.9 ± 8.1 ps group delay

A 21-27 GHz CMOS ultra-wideband low-noise amplifier (UWB LNA) with state-of-the-art phase linearity property (group delay variation is only ± 8.1 ps across the whole band) is reported for the first time. To achieve high and flat gain (S₂₁) and small group delay variation at the same time, the inductive series peaking technique was adopted in the output of each stage for bandwidth enhancement. The LNA dissipated 27 mW power and achieved input return loss (S₁₁) of 213 to 220.1 dB, output return loss (S₂₂) of 28.2 to 230.2 dB, flat S21 of 9.3 ± 1.3 dB, reverse isolation (S₁₂) of 252.7 to 273.3 dB, and noise figure of 4.9?6.1 dB over the 21-27 GHz band of interest. The measured 1 dB compression point (P_1dB) and input third-order intermodulation point (IIP3) were 214 and 24 dBm, respectively, at 24 GHz.     

3–10-GHz Ultra-Wideband Low-Noise Amplifier Utilizing Miller Effect and Inductive Shunt–Shunt Feedback Technique

In this paper, we demonstrate an SiGe HBT ultra-wideband (UWB) low-noise amplifier (LNA), achieved by a newly proposed methodology, which takes advantage of the Miller effect for UWB input impedance matching and the inductive shunt-shunt feedback technique for bandwidth extension by pole-zero cancellation. The SiGe UWB LNA dissipates 25.8-mW power and achieves S₁₁ below -10 dB for frequencies from 3 to 14 GHz (except for a small range from 10 to 11 GHz, which is below -9 dB), flat S₂₁ of 24.6 plusmn 1.5 dB for frequencies from 3 to 11.6 GHz, noise figure of 2.5 and 5.8 dB at 3 and 10 GHz, respectively, and good phase linearity property (group-delay variation is only plusmn28 ps across the entire band). The measured 1-dB compression point (P₁ dB) and input third-order intermodulation point are -25.5 and -17 dBm, respectively, at 5.4 GHz.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

Ultra-wideband SiGe low-noise amplifier

A low-noise amplifier (LNA) for ultra-wideband (UWB) is presented. The LNA, consisting of two gain stages in multiple feedback loops, achieves a flat power gain of a nominal 20 dB and a noise figure of 2.8-4.7 dB over the 3.1-10.6 GHz UWB band. Implemented in a 0.25 /spl mu/m SiGe BiCMOS process, the amplifier occupies 0.34 mm/sup 2/ and draws 11 mA from a 2.7 V supply.     

3．1～10．6GHz超宽带低噪声放大器的设计

基于SIMC0．18μmRFCMOS工艺技术,设计了可用于3．1—10．6GHzMB—OFDM超宽带接收机射频前端的CMOS低噪声放大器（LNA）。该LNA采用三级结构：第一级是共栅放大器,主要用来进行输入端的匹配;第二级是共源共栅放大器,用来在低频段提供较高的增益;第三级依然为共源共栅结构,用来在高频段提供较高的增益,从而补偿整个频带的增益使得增益平坦度更好。仿真结果表明：在电源电压为1．8v的条件下,所设计的LNA在3．1～10．6GHz的频带范围内增益（521）为20dB左右,具有很好的增益平坦性f±0．4dB）,回波损耗S11、S22均小于-10dB,噪声系数为4．5dB左右,IIP3为-5dBm,PIdB为0dBm。     

A Ultra-Wideband Amplitude Modulation (AM) Detector Using Schottky Barrier Diodes Fabricated in Foundry CMOS Technology

Utility of Schottky diodes fabricated in foundry digital 130-nm CMOS technology is demonstrated by implementing an ultra-wideband (UWB) amplitude modulation detector consisting of a low-noise amplifier (LNA), a Schottky diode rectifier, and a low-pass filter. The input and output matching of the detector is better than -10 dB from 0-10.3 GHz and 0-1.7 GHz, respectively, and almost covers the entire UWB frequency band (3.1-10.6 GHz). The measured peak conversion gain is -2.2dB. The sensitivity over the band for amplitude modulation with the minimum E _b/N_o of 6 dB is between -53 and -56 dBm. The power consumption is only 8.5 mW     

3-10 GHz low-power, low-noise CMOS distributed amplifier using splitting-load inductive peaking and noise-suppression techniques

A CMOS distributed amplifier (DA) with flat and low noise figure (NF), and flat and high gain (S ₂₁) is demonstrated. A flat and low NF was achieved by adopting a RL terminating network for the gate transmission line, and a slightly under-damped Q-factor for the second-order NF response. Besides, flat and high S ₂₁ was achieved using the proposed cascade gain cell, which constitutes a cascode-stage with a low-Q RLC load and a splitting-load inductive-peaking inverter stage. In the high-gain (HG) mode, the DA consumed 27.6 mW and achieved S ₂₁ of 17.5 plusmn 1.23 dB with an average NF of 3.24 dB over the 3-10 GHz band, one of the best reported NF performances for a CMOS UWB DA or LNA in the literature. The measured IIP3 was 2.1 dBm (at 8 GHz). In the low-gain (LG) mode, the DA achieved S ₂₁ of 10.74 plusmn 1.2 dB and an average NF of 4.67 dB with a low power dissipation of 9 mW.     

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-/spl mu/m 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7/spl plusmn/0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.     

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

S-band low noise amplifier using 1μm InGaAs/InAlAs/InP pHEMT

正This paper discusses the design of a wideband low noise amplifier(LNA) in which specific architecture decisions were made in consideration of system-on-chip implementation for radio-astronomy applications.The LNA design is based on a novel ultra-low noise InGaAs/InAlAs/InP pHEMT.Linear and non-linear modelling of this pHEMT has been used to design an LNA operating from 2 to 4 GHz.A common-drain in cascade with a common source inductive degeneration,broadband LNA topology is proposed for wideband applications.The proposed configuration achieved a maximum gain of 27 dB and a noise figure of 0.3 dB with a good input and output return loss(S_(11)—10 dB,S_(22)—11 dB).This LNA exhibits an input 1-dB compression point of-18 dBm,a third order input intercept point of 0 dBm and consumes 85 mW of power from a 1.8 V supply.     

A 1.2 V Reactive-Feedback 3.1–10.6 GHz Low-Noise Amplifier in 0.13 μm CMOS

A 15.1 dB gain, 2.1 dB (min.) noise figure low-noise amplifier (LNA) fabricated in 0.13 mum CMOS operates across the entire 3.1-10.6 GHz ultrawideband (UWB). Noise figure variation over the band is limited to 0.43 dB. Reactive (transformer) feedback reduces the noise figure, stabilizes the gain, and sets the terminal impedances over the desired bandwidth. It also provides a means of separating ESD protection circuitry from the RF input path. Bias current-reuse limits power consumption of the 0.87mm² IC to 9 mW from a 1.2 V supply. Comparable measured results are presented from both packaged and wafer probed test samples     

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain \(\hbox {S}_{21}\) of \(20.10 \pm 1.65\,\hbox {dB}\) across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, \(\hbox {S}_{11}\), lies below \(-\,10\) dB from 4.9–9.1 GHz frequency. Moreover, the output reflection (\(\hbox {S}_{22}\)) and reverse isolation (\(\hbox {S}_{12}\)), is below \(-\,10\) and \(-\,48\) dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure (\(\hbox {NF}_{min}\)) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of \(\pm \,0.45\,\hbox {dB}\) in its \(\hbox {NF}_{min}\) characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is \(-\,4.22\) dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of \(\pm \,115\,\hbox {ps}\) and \(\pm \,1.65\,\hbox {dB}\), respectively.     

1.5-6GHz增益和噪声系数稳定的两级超宽带CMOS低噪声放大器设计与性能模拟

 针对UWB应用设计实现了一个1.5-6GHz的两级CMOS低噪声放大器(LNA). 通过引入共栅(CG)和共源(CS)结构以获得宽范围内的输入匹配,采用电流镜和峰化电感进行电流复用,所提出的LNA实现了非常平坦化的功率增益和噪声系数(NF). 经标准0.18μm CMOS工艺实现后,版图后模拟结果表明在1.5-5GHz频率范围内功率增益(S21)为11.45±0.05dB,在2-6GHz频率范围内噪声系数(NF)为5.15±0.05dB,输入损耗(S11)小于-18dB. 在5GHz时,模拟得到的三阶交调点(IIP3)为-7dBm,1dB压缩点为-5dBm.在1.8V电源电压下,LNA消耗6mA的电流,版图实现面积仅为0.62mm^2.     

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18 μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6 GHz. The resonance points were set in 3 GHz and 10 GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S₂₁>10 dB) with a good input impedance matching less than –10 dB and a minimum noise figure of 2.9 dB over the entire band. The proposed UWB LNA consumed 15.2 mW from a 1.8 V power supply.     

0.2μm GaAs PHEMT3.1~10.6GHz宽带低噪声放大器设计

采用OMMIC公司提供的0.2μm GaAs PHEMT工艺(fT=60 GHz)设计并实现了一种适用于宽带无线通信系统接收前端的低噪声放大器。在3.1~10.6 GHz的频带内测试结果如下:最高增益为13 dB;增益波动<2dB;输入回波损耗S11<-11 dB;输出回波损耗S22<-16 dB;噪声系数NF<3.9 dB。5 V电源供电,功耗为120mW。芯片面积为0.5 mm×0.9 mm。与近期公开发表的宽带低噪声放大器测试结果相比较,本电路结构具有芯片面积小、工作带宽大、噪声系数低的优点。     

2～12 GHz CMOS超宽带低噪声放大器设计

提出了一种基于双反馈电流复用结构的新型CMOS超宽带(UWB)低噪声放大器(LNA),放大器工作在2～12 GHz的超宽带频段,详细分析了输入输出匹配、增益和噪声系数的性能。设计采用TSMC 0.18μm RF CMOS工艺,在1.4 V工作电压下,放大器的直流功耗约为13mW(包括缓冲级)。仿真结果表明,在2～12 GHz频带范围内,功率增益为15.6±1.4 dB,输入、输出回波损耗分别低于-10.4和-11.5 dB,噪声系数(NF)低于3 dB(最小值为1.96 dB),三阶交调点IIP3为-12 dBm,芯片版图面积约为712μm×614μm。     

Analysis, design, and optimization of InGaP-GaAs HBTmatched-impedance wide-band amplifiers with multiple feedback loops

The realization of matched impedance wide-band amplifiers fabricated by InGaP-GaAs heterojunction bipolar transistor (HBT) process is reported. The technique of multiple feedback loops was used to achieve terminal impedance matching and wide bandwidth simultaneously. The experimental results showed that a small signal gain of 16 dB and a 3-dB bandwidth of 11.6 GHz with in-band input/output return loss less than -10 dB were obtained. These values agreed well with those predicted from the analytic expressions that we derived for voltage gain, transimpedance gain, bandwidth, and input and output impedances. A general method for the determination of frequency responses of input/output return losses (or S₁₁, S₂₂) from the poles of voltage gain was proposed. The intrinsic overdamped characteristic of this amplifier was proved and emitter capacitive peaking was used to remedy this problem. The tradeoff between the input impedance matching and bandwidth was also found     

一种具有三陷波特性的超宽带印刷天线设计

提出了一种新型的具有三陷波特性的超宽带印刷天线。大钱形的辐射贴片和共面波导传输线馈电,可以保证在相当宽的3个频带内具有良好的阻抗匹配。回波损耗S₁₁＜-10 dB的阻抗带宽是3.1~10.6 GHz,除了其中3.3~3.7 GHz 的WiMAX,5.15~5.825 GHz的WLAN和7.25~8.4 GHz的X波段下行频段3个陷波频段。这些陷波的频段可以通过在天线的辐射贴片上增加长条裂缝和U形缝隙实现。加工和测试结果表明,该天线具有很好的阻抗带宽和全向辐射方向图。