Reducing test application time, test data volume and test power through Virtual Chain Partition

A new scan approach is described, named ‘Virtual Chain Partition’ (VCP) architecture, capable of substantially reducing the test application time, test data volume and test power. The VCP architecture maintains the original scan cell order. A simple procedure is proposed, which uses the scan test set generated for the original circuit to determine the maximum reduction in test cycles obtainable with the architecture and to select the most suitable configuration for each circuit. The experiments carried out with the ISCAS 89 benchmarks show that the VCP architecture allows considerable reductions to be achieved both for single and multiple scan chain circuits.     

Split variable-length input Huffman code with application to test data compression for embedded cores in SOCs

In this article, a run length encoding-based test data compression technique has been addressed. The scheme performs Huffman coding on different parts of the test data file separately. It has been observed that up to a 6% improvement in compression ratio and a 29% improvement in test application time can be achieved sacrificing only about 6.5% of the decoder area. We have compared our results with the other contemporary works reported in the literature. It has been observed that for most of the cases, our scheme produces a better compression ratio and that the area requirements are much less.     

Test data compression using alternating variable run-length code

This paper presents a unified test data compression approach, which simultaneously reduces test data volume, scan power consumption and test application time for a system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length (AVR) codes for test data compression. A formal analysis of scan power consumption and test application time is presented. The analysis showed that a careful mapping of the don’t-cares in pre-computed test sets to 1s and 0s led to significant savings in peak and average power consumption, without requiring slower scan clocks. The proposed technique also reduced testing time compared to a conventional scan-based scheme. The alternating variable run-length codes can efficiently compress the data streams that are composed of both runs 0s and 1s. The decompression architecture was also presented in this paper. Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases.     

Test response reuse-based SoC core test compression and test scheduling for test application time minimization

This paper presents a novel approach to system-on-a-chip (SoC) core test compression and test scheduling. Every test set is compressed through the test responses of its preceding core in preprocessing step by simulation. Consequently, under our method the test sets contain two parts: (1) the test sets that are compatible with the test responses of their individual preceding cores. This part can be removed from their original test sets, and (2) the test sets that none of the test vectors from them are compatible with the test responses of their individual preceding cores. On hardware implementation, only a couple of 2-1 MUXs are needed. The algorithms for reordering the sequences of core-under-tests and those of the test vectors for each corresponding core are outlined for optimal test compression results. It needs neither coder nor decoder, thus saving hardware overhead. Power-constrained SoC core test pipelining consumes less test application time. Hierarchical clustering-based SoC test scheduling can be implemented easily, and the hardware overhead is negligible. Experimental results on benchmark ISCAS 89 demonstrate that our method achieves significant improvement of test time and less ATE requirement over the previous methods, and it does not discount the fault coverage of each test set, moreover, the fault coverage for some test sets is improved instead.     

Self-test of sequential circuits with deterministic test pattern sequences

This article describes a new approach for synthesizing a cost-efficient self-test hardware for a given set of deterministic test pattern sequences. To minimize the test hardware effort instead of all the test sequences, only a very small subset will be selected such that a simple generation of all necessary test sequences will be ensured. This procedure drastically decreases the storage requirements (about 80%) and therefore distinctly reduces the necessary test hardware overhead. Experimental results on the ISCAS-S-benchmarks emphasize the efficiency of our approach.This work is supported by the ESPRIT project 6855 (LINK).     

A new scheme of test data compression based on equal-run-length coding (ERLC)

A new scheme of test data compression based on run-length, namely equal-run-length coding (ERLC) is presented. It is based on both types of runs of 0's and 1's and explores the relationship between two consecutive runs. It uses a shorter codeword to represent the whole second run of two equal length consecutive runs. A scheme for filling the don't-care bits is proposed to maximize the number of consecutive equal-length runs. Compared with other already known schemes, the proposed scheme achieves higher compression ratio with low area overhead. The merits of the proposed algorithm are experimentally verified on the larger examples of the ISCAS89 benchmark circuits.     

CMOS图像传感器片上系统及其在手机上的应用

带相机功能的手机越来越流行并逐渐成为手机的标准配置。CMOS图像传感器因其在低成本、图像效果好、低功耗、集成度高等方面的优势,在手机市场上逐渐成为主流。随着功能与集成度的提高,片上系统与单芯片方案已经成为一个趋势。介绍CMOS图像传感器片上系统的架构与原理、图像信号处理模块,然后给出他在手机系统上的应用与软件实现。     

一种改进的高速彩票总线仲裁器

随着半导体工艺的发展,片上系统(System-on-Chip, SoC)内部集成的不同功能IP(Intellectual Property)核越来越多。各IP核通过总线方式连接,多核同时抢占总线很大地制约了片上系统的性能。高效的总线仲裁器可以解决多核抢占总线引起的冲突和竞争问题,提升片上系统性能。该文提出一种改进的高速彩票总线仲裁器。使用4相双轨协议代替时钟实现彩票抽取机制以防止彩票丢弃,采用异步流水线交叉并行的工作方式以提升工作速度。在NINP(NonIdling and NonPreemptive)模型下通过65 nm CMOS工艺的Xilinx Virtex5板级验证,相比经典彩票仲裁器和动态自适应彩票仲裁器,具有更好的带宽分配功能,有效避免撑死和饿死现象,工作速度提高49.2%以上,具有一定的功耗优势,适用于有速度要求的多核片上系统。     

面向SoC任务分配的应用程序存储需求量分析方法

通过分析应用程序的存储需求量,辅助片上系统(System-on-Chip, SoC)任务分配进行数据存储与传输优化,是改善SoC性能的途径之一.目前,存储需求量分析方法的分析粒度单一、速度缓慢,不利于进行多粒度任务分配空间的高效探索.本文面向SoC任务分配,提出一种多粒度、快速存储需求量分析方法.该方法可进行多粒度的存储需求量分析,并针对多媒体程序,引入数组数据域划分技巧,大幅度减少了存储需求量的分析时间.     

FPGA硬核处理器系统加速数字电路功能验证的方法

为了缩短专用集成电路和片上系统的功能验证周期,该文提出FPGA硬核处理器系统加速数字电路功能验证的方法。所提方法综合软件仿真功能验证和现场可编程门阵列原型验证的优点,利用集成在片上系统现场可编程门阵列器件中的硬核处理器系统作为验证激励发生单元和功能验证覆盖率分析单元,解决了验证速度和灵活性不能统一的问题。与软件仿真验证相比,所提方法可以有效缩短数字电路的功能验证时间;在功能验证效率和验证知识产权可重用方面表现优于现有的FPGA原型验证技术。     

Review of advanced FPGA architectures and technologies

Field Programmable Gate Array （FPGA） is an efficient reconfigurable integrated circuit platform and has become a core signal processing mieroehip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system inte- gration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, intercon- nects, and embedded resources. Moreover, some important emerging design issues of FPGA archi- tectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.     

基于FDR码改进分组的SoC测试数据压缩方法

文章提出一种基于FDR码改进分组的SoC测试数据压缩方法.经过对原始测试集无关位的简单预处理,提高确定位0在游程中的出现频率.在FDR码的基础上,改进其分组方式,通过理论证明其压缩率略高于FDR编码,尤其是短游程的压缩率.用C语言编写程序模拟两种编码方法的软件实现程序,实验结果证明了改进分组的FDR编码方法的有效性和高压缩性.     

A test set embedding approach based on twisted-ring counter with few seeds

Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS’89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.     

联体式综合环境试验箱的选型和应用

对联体式综合环境试验箱的选型和应用情况进行了介绍,包括技术需求、方案、可行性、具体的结构形式和控制方式、应用方式以及应用事例等。联体式综合环境试验箱的选型,实现了综合环境试验箱的多种组合应用方式,能够满足系统级、多剖面综合环境可靠性试验的需求。     

ATE测试成本优化

多点测试是降低片上系统测试成本的有效手段,目前支持多点测试的ATE(自动测试设备)越来越多。多点测试通过并行测试多个芯片降低了测试成本,但是如何选择多点测试使得测试成本最低,需要综合考虑多方面因素,包括ATE成本、芯片的测试策略等。文中从ATE出发,建立芯片的测试成本模型,通过该模型获得了最佳测试方案。     

CTA8280集成电路测试系统的研究应用

集成电路测试系统对测试精度、测试速度、测试功能等方面提出了越来越高的要求,测试系统并行测试和乒乓测试结合可以更好地利用现有的硬件资源,最大限度地提高系统的测试效率,降低测试成本。针对CTA8280测试系统结构、关键技术、应用案例进行分析介绍。     

复用NoC测试IP芯核测试存取链优化配置

论述了层次型IP芯核不同测试模式之间的约束关系,给出了层次型IP芯核的测试壳结构,提出了一种复用片上网络测试内嵌IP芯核的启发式测试存取链优化配置方法.该方法可有效减小测试数据分组数量和被测芯核的测试时间.使用片上网络测试平台,在测试基准电路集ITC'02中的基准电路p22810上进行了实验验证.     

TMS320F28XX系列DSP测试方法研究与实现

本项目是基于美国TI公司TMS320F28xx系列DSP,进行的测试方法研究与实现。测试方法用于北京自动测试技术研究所自主研发的国产自测试设备（ATE）BC3192V50大规模集成电路测试系统。测试的原理是,通过TMS320F28xx系列DSP配备的SCI（Serial Communication Interface)串行通信接口,以此作为桥梁完成ATE与芯片之间的通信。同时,实现自动测试设备与测试系统的测试向量的匹配。而后,完成TMS320F28xx系列DSP的功能测试以及直流参数测试。     

系统芯片的可测性设计与测试

阐述了系统芯片(SoC)测试相比传统IC测试的困难,SoC可测性设计与测试结构模型,包括测试存取配置、芯核外测试层,以及测试激励源与测试响应汇聚及其配置特性、实现方法与学术研究进展,介绍了基于可复用内嵌芯核的SoC国际测试标准IEEE P1500的相关规约;最后,建议了在SoC可测性设计及测试中需要密切关注的几个理论问题。     

试论电子计算机在瞬间测试中的应用

文章首先对电子计算机进行了简介,进分析了电子计算机在液体发射药装置瞬间测试中的应用,最后还以液体发射药试验装置的瞬间测试为例对电子计算机的控制原理实施方案进行了介绍.