SiGe BiCMOS technology for RF circuit applications

SiGe BiCMOS is reviewed with focus on today's production 0.18-/spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/, as well as lower power consumption, noise figure, and improved large-signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high-power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz).     

Fabrication, RE performance, and yield of a combined limitingamplifier and dual-modulus prescalar GaAs IC chip

Production technology details, RF performance, and yield results for an ECL-compatible, L-band, limiting dual-modulus (÷10/11) prescalar are presented. Monolithic integration of analog and digital circuit functions is achieved using refractory self-aligned-gate FET technology. When tested with -22-dBm input signal power, one lot of six wafers had a total RF chip yield of 19% with a best-wafer yield of 43%. The average operating frequency was 1.45 GHz (SD=51 MHz) with an average power dissipation of 696 mW (SD=23 mW)     

基于混合集成的高增益光接收模块北大核心

针对光载无线通信(RoF)系统对高增益、小型化光接收模块(ROSA)的需求,基于混合集成技术,设计并制作了一种高增益的四通道ROSA器件,尺寸为20.0 mm×14.0 mm×5.9 mm。模块内集成了低噪声放大器(LNA)芯片以提高射频信号增益,建立了射频信号传输电路,并对器件特性进行了仿真分析。经测试,器件的射频信号增益达14 dB,-3 dB带宽为23 GHz,在1550 nm波长的入射光下,器件的响应度为0.81 A/W,相邻信道之间的射频信号串扰小于-40 dB。该模块对于减小RoF系统的体积和功耗具有重要意义。     

A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I—ESD

Electrostatic discharge (ESD) continues to be a semiconductor quality and reliability area of interest as semiconductor components are reduced to smaller dimensions. The combination of scaling, design integration, circuit performance objectives, new applications, and the evolving system environments, ESD robustness will continue to be a technology concern. With the transition from silicon bipolar junction transistor to modern BiCMOS silicon germanium (SiGe) semiconductor technologies, new semiconductor process and integration issues have evolved which influence both device performance and ESD protection. Additionally, the issues of low cost, low power and radio frequency (RF) GHz performance objectives has lead to both revolutionary as well as derivative technologies; these have opened new doors for discovery, development and research in the area of on-chip ESD protection and design. With the growth of interest of ESD in RF technology, new innovations and inventions are occurring at a rapid pace. In this paper, we will provide an introductory review of silicon germanium technology and ESD.     

SiGe PMOSFET性能模拟

由于受热力学基本定律的限制 ,Si集成电路技术的发展已经日益接近极限 ,而 Si Ge材料的引入使得占据小于 1GHz频段的 Si产品可以进一步覆盖 2～ 30 GHz的 RF和无线通信市场。根据前人的材料研究工作 ,在普通 Si器件性能模拟的基础上 ,进一步研究长沟应变 Si Ge器件的模拟 ,引入了插值所得的近似因子以修正 silvaco中隐含的 Si Ge能带模型和迁移率参数。然后依据修正后的模型对 Si Ge PMOS进行更为精确的二维模拟     

Device and technology evolution for Si-based RF integrated circuits

The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.     

An RF model of the accumulation-mode MOS varactor valid in both accumulation and depletion regions

This work presents an RF model of an accumulation-mode MOS varactor with physical lumped elements derived from the device structure. The channel resistance was modeled by three resistance components to cover both accumulation and depletion regions with single equivalent circuit. With parameter values obtained by direct extraction, this model could accurately describe characteristics of the device without any optimization steps in the frequency range up to 18 GHz, as well as over a wide bias range. Due to the single topology, easy integration of the model into common circuit simulators is possible.     

Moving average filter for spur reduction in subsampling fractional PLLs

A mono-bit digital receiver circuit for instantaneous frequency measurement is presented. The circuit is co-designed with Indium Phosphide Double Heterojunction Bipolar Transistor and complementary metal oxide semiconductor (CMOS) devices. The chip is fabricated by InP/CMOS three-dimensional (3D) heterogeneous integration using the wafer-level bonding technique. The measurable signal frequency within?+?15 to???25 dBm power is up to 7.5 GHz with a 14-GHz clock. Compared to an integrated circuit (IC) with a traditional InP or CMOS technologies, the proposed chip could benefit from both InP and CMOS technology. In the heterogeneous integration, InP devices provide high operating frequency, broad signal bandwidth, and large input signal dynamic range, while CMOS devices achieve complex function with low power consumption. In this way, the system FoM is improved for a mono-bit digital receiver while the system power consumption is kept the same. This work also shows the great potential of the 3D heterogeneous integration for the high-performance mixed-signal and multifunction radio-frequency ICs.

     

Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed S-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection scheme and the impact of the parasitics associated with the protection devices. It is shown that a four-stage distributed ESD protection can be beneficial for frequencies up to 10 GHz. In addition, two generalized design optimization methodologies incorporating coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range (0-10 GHz). By using this optimized design, an ESD device with a parasitic capacitance of 200 fF attenuates the RF signal power by only 0.27 dB at 10 GHz. Furthermore, termination schemes are proposed to allow this analysis to be applicable to high-speed digital and mixed-signal systems.     

基于SiGe工艺的高增益射频功率放大器

基于0.13μm SiGe HBT工艺,设计应用于无线局域网(WLAN)802.11b/g频段范围内的高增益射频功率放大器.该功放工作在AB类,由三级放大电路级联构成,并带有温度补偿和线性化的偏置电路.仿真结果显示:功率增益高达30dB,1dB压缩点输出功率为24dBm,电路的S参数S11在1.5～4GHz大的频率范围内均小于-17dB,S21大于30dB,输出匹配S22小于-10dB,S12小于-90dB.最高效率可达42.7%,1dB压缩点效率为37%.     

AC floating-body effects in submicron fully depleted (FD) SOInMOSFETs and the impact on analog applications

We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications     

一种射频可编程N分频器的设计

提出了用射频CML技术设计的2/3分频单元.基于2/3分频单元,使用0.35 μm SiGeBiCMOS工艺,实现了射频可编程N分频器.验证结果表明,电路可在GHz频率下正常工作,具有相噪低、功耗小等特点.在3 GHz射频输入信号频率下,频偏100 kHz的输出相位噪声为-143dBc/Hz.电路消耗的总电流仅为4 mA(3 V单电源电压),功耗仅为12 mW.     

A highly integrated multifunction macro synthesizer chip (MMSC) forapplications in 2-18 GHz synthesized sources

A highly integrated monolithic microwave integrated circuit (MMIC) that acts as the core of the RF section of a synthesized source is developed using commercially available 0.2-μm pseudomorphic high electron mobility transistor (PHEMT) technology. Measured performance is shown up to 18 GHz. The same system architecture is able to produce synthesized output through 40 GHz with modifications of some critical building blocks of the chip. The chip performs all the frequency selection and tuning functions. It has more than 30 RF blocks integrated on an area of 4.27×4.68 mml. Some individual blocks operate through 40 GHz     

A 60-GHz uniplanar MMIC 4/spl times/ subharmonic mixer

A uniplanar GaAs monolithic microwave integrated circuit /spl times/4 subharmonic mixer (SHM) has been fabricated for 60-GHz-band applications using an antiparallel diode pair in finite ground coplanar (FGC) waveguide technology. This mixer is designed to operate at an RF of 58.5-60.5 GHz, an IF of 1.5-2.5 GHz, and an LO frequency of 14-14.5 GHz. FGC transmission-line structures used in the mixer implementation were fully characterized using full-wave electromagnetic simulations and on-wafer measurements. Of several mixer configurations tested, the best results show a maximum conversion loss of 13.2 dB over the specified frequency range with a minimum local-oscillator power of 3 dBm. The minimum upper sideband conversion loss is 11.3 dB at an RF of 58.5 GHz and an IF of 2.5 GHz. This represents excellent performance for a 4/spl times/ SHM operating at 60 GHz.     

微波功率器件的滤波器测试电路

在微波电路原理和半导体器件物理的基础上,设计和模拟了三种用于微波功率器件的测试电路,并且设计了与之配套的测试夹具.采用矢量网络分析仪对该测试电路和夹具,在3～8GHz范围内进行了小信号测试.模拟和测试结果表明,采用阶梯阻抗滤波器偏置网络的测试电路性能较好,比采用扇形线偏置网络的测试电路具有更宽的带宽.该滤波器偏置电路能够用来在整个C波段,即在4～8GHz内对微波功率器件进行测试.但是,微带叉指耦合电容没有起到取代贴片隔直电容的目的,原因是该结构对参数精度要求高,而PCB制作工艺无法满足这个要求.     

High-performance oscillators and power combiners with InP Gunn devices at 260-330 GHz

InP Gunn devices with graded doping profiles were evaluated for second-harmonic power extraction above 260 GHz. The best devices generated radio frequency(RF) output power levels of 3.9 mW at 275 GHz, 4.8 mW at 282 GHz, 3.7 mW at 297 GHz, 1.6 mW at 329 GHz, and 0.7 mW at 333 GHz with corresponding dc-to-RF conversion efficiencies of 0.24%, 0.31%, 0.32%, 0.19%, and 0.07%. The highest observed second-harmonic frequency was 345 GHz. Two devices each in an in-line power combining circuit generated 6.1 mW at 285 GHz and 2.7 mW at 316 GHz with combining efficiencies of more than 65%.     

Low-K/Cu CMOS-based SoC technology with 115-GHz f/sub T/, 100-GHz f/sub max/, low noise 80-nm RF CMOS, high-Q MiM capacitor, and spiral Cu inductor

Logic CMOS-based RF technology is introduced for a 10-Gb transceiver in which active and passive RF devices have been realized in a single chip. RF nMOS of 115-GHz f/sub T/, 100-GHz f/sub max/, and sub-1.0-dB NF/sub min/ at 10 GHz have been fabricated by aggressive device scaling and layout optimization. High-Q MiM capacitor and spiral Cu inductors have been successfully implemented in the same chip by 0.13-/spl mu/m low-K/Cu back end of integration line technology. Core 1.0 V MOS and/or junction varactors for VCO at 10 GHz are offerings free of extra cost and realized by the elaborated layout.     

An Active Recursive RF Filter in 0.35 μm BiCMOS

An active recursive filter approach is proposed for the implementaion of an inductorless, tuneable RF filter in BiCMOS. A test circuit was designed and manufactured in a 0.35 μm SiGe BiCMOS technology. In simulations, the feasibility of this type of filter was demonstrated and reasonably good performance was obtained. The simulations show a center frequency tuning range from 6 to 9.4 GHz and a noise figure of 8.8 to 10.4 dB depending on center frequency. Gain and Q-value are tunable in a wide range. Simulated IIP-3 and 1-dB compression point is ?26 and ?34 dBm respectively, simulated at the center frequency 8.5 GHz and with 15 dB gain. Measurements on the fabricated device shows a center frequency tuning range from 6.6 to 10 GHz, i.e. slightly higher center frequencies were measured than the simulated.     

Submillimeter-wave InP Gunn devices

Recent advances in design and technology significantly improved the performance of low-noise InP Gunn devices in oscillators first at D-band (110-170 GHz) and then at W-band (75-110 GHz) frequencies. More importantly, they next resulted in orders of magnitude higher RF output power levels above D-band and operation in a second-harmonic mode up to at least 325 GHz. Examples of the state-of-the-art performance are continuous-wave RF power levels of more than 30 mW at 193 GHz, more than 3.5 mW at 300 GHz, and more than 2 mW at 315 GHz. The dc power requirements of these oscillators compare favorably with those of RF sources driving frequency multiplier chains to reach the same output RF power levels and frequencies. Two different types of doping profiles, a graded profile and one with a doping notch at the cathode, are prime candidates for operation at submillimeter-wave frequencies. Generation of significant RF power levels from InP Gunn devices with these optimized doping profiles is predicted up to at least 500 GHz and the performance predictions for the two different types of doping profiles are compared.     

Microwave and millimeter-wave QWITT diode oscillators

The authors present DC, microwave, and millimeter-wave characteristics of different quantum-well-injection transit-time (QWITT) devices. Small-signal and large-signal device models are used to provide physical design parameters to maximize the output power density at any desired frequency of operation. A peak output power density of 3.5-5 kW/cm² in the frequency range 5-8 GHz has been obtained from a planar QWITT oscillator. This appears to be the highest output power density obtained from any quantum-well oscillator at any frequency. This result also represents the first planar circuit implementation of a quantum-well oscillator. Good qualitative agreement between DC and RF characteristics of QWITT devices and theoretical predictions based on small-signal and large-signal analyses is achieved. The device efficiency has been increased from 3% to 5% by optimizing the design of the drift region in the device through the use of a doping spike with optimized concentration, without compromising the output power at X -band. Self-oscillating QWITT diode mixers are also demonstrated at X-band in both waveguide and planar circuits. The self-oscillating mixer exhibits a conversion gain of about 10 dB in a narrow bandwidth and a conversion loss of about 5 dB if broadband operation is desired