一种低功耗245GHz次谐波接收机

介绍了一种应用于气体频谱分析传感器的低功耗245 GHz次谐波接收机,该接收机具有低功耗、高线性度和高集成度的特点.该接收机由四级共基极低噪声放大器、二次次谐波无源反接并联二极管对(APDP)混频器、120GHz推推型压控振荡器-分频器链路、120 GHz功率放大器和中频放大器构成,采用了特征频率为300 GHz、最大振荡频率为500 GHz的锗硅BiCMOS工艺实现.该接收机芯片实现了10.6 dB的转换增益和13 GHz的带宽,噪声系数为20 dB,输入1dB压缩点仿真结果为-9 dBm,接收机如果不包括120 GHz压控振荡器-功率放大器链路功耗为99.6 mW,接收机包括120 GHz压控振荡器-功率放大器链路功耗为312 mW.     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

A 94 GHz planar monopulse tracking receiver

This paper describes the design, fabrication and measurements of a 94 GHz integrated monopulse receiver with IF beam control. The receiver is integrated on a single chip, and is based on a 23 GHz local oscillator driving four separate phase-coherent 94 GHz subharmonic mixers. The resulting IF signals are takeoff-chip to a IF monopulse processor, which produces sum and difference monopulse patterns for the elevation and azimuth coordinates. Voltage-controlled phase-shifters in each of the IF channels allow the monopulse patterns to be electronically steered. All of the receiver circuits are realized using uniplanar coplanar-waveguide (CPW), slot lines and coplanar striplines (CPS). These features result in a compact, low-cost system suitable for tracking systems operating in poor visibility conditions, as well as in collision avoidance receivers for automotive applications. To our knowledge, this work represents the first demonstration of a fully integrated millimeter-wave subsystem to date     

A 250 GHz planar low noise Schottky receiver

A planar quasi-optical Schottky receiver based on the quasi-integrated horn antenna has been developed and tested over the 230–280GHz bandwidth. The receiver consists of a planar GaAs Schottky diode placed at the feed of a dipole-probe suspended on a thin dielectric membrane in an etched-pyramidal horn cavity. The diode has a 1.2Μm anode diameter and a low parasitic capacitance due to the use of an etched surface channel. The antenna-mixer results in a measured DSB conversion loss and noise temperature at 258GHz of 7.2dB±0.5dB and 1310K±70K, respectively, at room temperature. The design is compatible with SIS mixers, and the low cost of fabrication and simplicity makes it ideal for submillimeter-wave imaging arrays requiring a 10–20% bandwidth.     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

A wideband low-noise amplifier (LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth,the input third intercept point (IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

正A wideband low-noise amplifier(LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth, the input third intercept point(IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

A very low-noise receiver for 80–120 GHz

A new dual-polarized cryogenic Schottky barrier mixer receiver for radio astronomy applications is described. Between 85 and 120 GHz, the double sideband receiver temperature, including all contributions from the polarization diplexing system, telescope coupling optics and dewar window is less than 125°K in either channel. Novel features include a very broadband, fixed tuned mixer design and a compact, low-loss, linear polarization diplexing scheme.     

A planar subharmonically-pumped 71 GHz receiver with integral feed antenna

A planar, subharmonically-pumped, hybrid millimeter-wave receiver with integral antenna is described. Coplanar waveguide filters are used to isolate the ports and provide image enhancement. The integral planar antenna has 12 dB gain and is suited for use as a feed. The main lobe is normal to the substrate surface. The receiver is designed for an instantaneous bandwidth of 10 GHz. Experiments at 71 GHz indicate single-sideband mixer conversion loss of 6.5 dB. We believe that this represents the highest level of integration yet demonstrated in this frequency range.     

A 140-170-GHz low-noise uniplanar subharmonic Schottky receiver

A 150-GHz Schottky diode subharmonic receiver based on a coplanar-waveguide-fed double-folded-slot (DFS) antenna is presented in this paper. The DFS antenna is placed on an extended hemispherical high-resistivity silicon substrate lens to achieve a high directivity and a high coupling to a Gaussian beam efficiency. The uniplanar receiver results in a 12±0.5-dB measured double-sideband conversion loss at 144-152 GHz for a 8-10 mW local-oscillator power at 77 GHz, and has a wide-hand ⩽13-dB conversion loss over 30 GHz of bandwidth (140-170 GHz). The measured conversion loss includes silicon lens absorption and reflection losses, as well as IF mismatch losses. The applications are in new small aperture (7.5-cm lenses) collision-avoidance radars at 150 GHz     

A frequency doubler for 200 GHz with a planar Schottky varactor

A frequency doubler for 200 GHz utilising a planar surface channel Schottky varactor was designed, constructed and tested. The doubler employes novel split-waveguide mount design with two sliding backshorts at both input and output waveguides. The theoretical maximum efficiency of the doubler is 44.0 % with input power level of 32 mW and the maximum output power is 16.5 mW with input power level of 50 mW. The measured maximum efficiency of the doubler was 7.1 % and the maximum output power was 2.6 mW     

A 4-9 GHz 10 W wideband power amplifier

A 4-9 GHz wideband high power amplifier is designed and fabricated, which has demonstrated saturated output power of 10 W covering 6-8 GHz band, and above 6 W over the other band. This PA module uses a bal-ance configuration, and presents power gain of 7.3 ± 0.9 dB over the whole 4-9 GHz band and 39% power-added efficiency (PAE) at 8 GHz. Both the input and output VSWR are also excellent, which are bellow -10 dB.     

New wideband high-gain stripline planar array for 12 GHz satellite TV

A new type of stripline planar array has been studied for 12 GHz satellite TV reception. A 16-element experimental antenna (dimensions?98×98×18 mm3), using a stripline corporate feed, presents a 2 : 1 VSWR bandwidth of over 2 GHz and a gain higher than 20.6 dBi in the 11.7?12.5 GHz bandwidth.     

一款25~45 GHz宽带MMIC低噪声放大器

基于砷化镓(GaAs)赝晶型高电子迁移率晶体管(PHEMT)工艺,研制了一款25~45 GHz宽带单片微波集成电路(MMIC)低噪声放大器。该放大器采用三级级联的双电源结构,前两级在确保良好的输入回波损耗的同时优化了放大器的噪声;末级采用最大增益的匹配方式,保证了良好的增益平坦度、输出端口回波损耗以及输出功率。此外还对源电感和宽带匹配都进行了优化,实现了低噪声下的宽带输出。在片测试表明,在栅、漏偏置电压分别为-0.38 V和3 V,电流为60 mA的工作条件下,该放大器在25~45 GHz频带内噪声系数小于2 dB,增益为(22±1.5) dB,输入、输出电压驻波比典型值为2:1,1 dB增益压缩输出功率(P－1 dB)典型值为10 dBm。该低噪声放大器可以用于宽带毫米波收发系统。     

A 4–9 GHz 10W wideband power amplifier

A 4-9 GHz wideband high power amplifier is designed and fabricated, which has demonstrated saturated output power of 10 W covering 6-8 GHz band, and above 6 W over the other band. This PA module uses a balance configuration, and presents power gain of 7.3 ＋ 0.9 dB over the whole 4-9 GHz band and 39% power-added efficiency （PAE） at 8 GHz. Both the input and output VSWR are also excellent, which are bellow -10 dB.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

一种用于3.1–4.8GHz MB-OFDM 超宽带系统的CMOS接收机

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的全集成全差分CMOS接收机芯片。在接收机射频前端中应用了一种增益可变的低噪声放大器和合并结构的正交混频器。在I/Q中频通路中则集成了5阶Gm-C结构的有源低通滤波器以及可变增益放大器。芯片通过Jazz 0.18μm RF CMOS工艺流片,含ESD保护电路。该接收机最大电压增益为65dB,增益可调范围为45dB,步长6dB;接收机在3个频段的平均噪声系数为6.4-8.8dB,带内输入三阶交调量(IIP3)为-5.1dBm。芯片面积为2.3平方毫米,在1.8V电压下,包括测试缓冲电路和数字模块在内的总电流为110mA。     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

Tunerless mixer mount for an SIS 80–120 GHz receiver

We have developed a 100 GHz band SIS receiver using a simple mixer mount design, which does not use variable RF tuning elements, such as a back short tuner or an E-plane tuner. The mixer mount structure was designed using calculations of the embedding impedance of the mixer mount, and of receiver performance, using the quantum theory of mixing under the 3-port approximation. The mixer mount structure we designed has a 1/7 reduced height waveguide and a “back short cavity”. We have constructed a receiver system using this tunerless mixer mount design, and we have measured the receiver noise temperatures for two different tunerless mixer mounts using arrays of four Nb/Al-AlOx/Nb junctions. For one of the two mixer mounts, we obtained very low noise receiver temperatures, 35–70 K, over the very wide frequency range of 80–120 GHz. We also show that, due to IF missmatching, the noise of the IF amplifier is the main contributor to the receiver noise temperature. We also compared the results of measurements with the results of our theoretical calculations. Our calculations reproduced the tendency of receiver performances very well. This tunerless mixer mount has application on the MM-Wave Array and in the multi-beam receiver.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.