等价性验证在Soc设计中的应用

本文介绍了仿真验证与形式验证的功能,重点讨论了等价性验证在soc设计中的应用及基本流程,分析了等价性验证过程中常遇到的一些问题并给出了解决方案,实验显示,该验证方法可准确快速的发现设计的错误,提高验证效率。     

Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using Sandia Controllability and Observability Program (SCOAP) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits

Application of Deterministic Logic BIST on Industrial Circuits

We present the application of a deterministic logic BIST scheme based on bit-flipping on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5–15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.     

Modeling Custom Digital Circuits for Test

Models meant for logic verification and simulation are often used for Automatic Test Pattern Generation (ATPG). For custom digital circuits, these models contain many tristate devices that tend to lower coverage for stuck-faults. Additionally, these tristate devices contribute to increased ATPG runtimes, fewer generated test sequences, and an overall lower test quality. The circuit under test is partitioned into channel connected sub-networks (CCSN) that consist of transistors that are connected at their source or drain terminals, except when these terminals are power, ground or primary inputs. Unlike other published work, algorithms presented in this paper analyze each CCSN in the context of its environment, thereby capturing the logical relationships among its input signals. Other algorithms presented include identification and modeling of embedded latches, clock generators and memory circuits. An abstract array model for memory that reduces the size of the model and increases simulation speed is also presented. When one specific feature of the algorithm was disabled, experimental results showed higher ATPG runtimes of about 35%, and an average decrease in fault coverage of around 15–20%. For the largest data cache, the memory modeling algorithm decreased the number of primitives from 1.23 million to 139 thousand.     

时序电路的形式化证明

对硬件的形式化验证是硬件验证的一个发展方向,形式化验证一个时序电路就是证明电路的实现是否满足他的规格描述.本文提出了用等式逻辑ε的一个公式Ws来表示电路的实现,用Tempura的程序B表示对该电路的特性描述.公式B（∈）P引入来证明电路的正确性,这里P是电路的初始状态,是从Ws中抽取的,另外还要从Ws提取输出等式.这样,一旦证明了B（∈）P,就能证明实现满足规格描述.最后,给出了一个例子来说明此证明方法.     

一种用于密码协议形式化验证的简单逻辑

给出了一个可用于密码协议形式化验证与设计的简单逻辑.该逻辑采用抽象的通道概念表示具有多种安全特性的通信链路,可在比现有认证逻辑的更抽象的层次上对协议进行处理.     

面向SoC系统芯片中跨时钟域设计的 模型检验方法

 传统方法无法在RTL验证阶段全面验证SoC系统芯片中的跨时钟域设计.为解决此问题,本文首先提出描述亚稳态现象的等价电路实现,用以在RTL验证中准确体现亚稳态现象的实际影响;然后使用线性时序逻辑对跨时钟域设计进行设计规范的描述;为缓解模型检验的空间爆炸问题,进一步针对跨时钟域设计的特点提出基于输入信号的迁移关系分组策略和基于数学归纳的优化策略.实验结果表明本文提出的方法不仅可以在RTL验证阶段有效地发现跨时钟域设计的功能错误,而且可以使验证时间随实验用例中寄存器数量的递增趋势从近似指数级增长减小到近似多项式级增长.     

An Efficient and Fast Area Optimization Approach for Mixed Polarity Reed-Muller Logic Circuits

Area has become one of the main bottlenecks restricting the development of integrated circuits.The area optimization approaches of existing XNOR/OR-based mixed polarity Reed-Muller(MPRM)circuits have poor optimization effect and efficiency.Given that the area optimization of MPRM logic circuits is a combinatorial opti-mization problem,we propose a whole annealing adaptive bacterial foraging algorithm(WAA-BFA),which includes individual evolution based on Markov chain and Metropolis acceptance criteria,and individual mutation based on adaptive probability.To address the issue of low conversion efficiency in existing polarity conversion approaches,we introduce a fast polarity conversion algorithm(FPCA).Moreover,we present an MPRM circuits area optimization approach that uses the FPCA and WAA-BFA to search for the best polarity corresponding to the minimum circuits area.Experimental results demonstrate that the proposed MPRM circuits area optimization approach is effective and can be used as a promising EDA tool.     

一种推广化符号轨迹赋值中伪报错的改进算法

介绍了推广化符号轨迹赋值中常用的模型检验强可满足性算法,分析了产生伪报错的原因,提出了一种降低伪报错的改进算法.该算法在前算法的基础之上减少了边的计算量,降低了由于抽象带来的伪报错问题,从而大大提高了计算过程中的准确率.实验结果表明,该改进算法在降低伪报错和减少计算量方面有明显提高.     

G-vector: A New Model for Glitch Analysis in Logic Circuits

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model.     

A Current-Mode Logic for Low-Voltage, High-Speed Mixed-Mode VLSI Circuits

A wired-AND current-mode logic (WCML) circuit is designed for high performance mixed analog and digital system designs on a common silicon substrate, using standard CMOS process. Current is used for digital information carrier in order to be able to reduce supply voltage, power consumption, digital switching noise and to increase operating frequency. The WCML circuit uses current-steering technique. It is composed of a simple current mirror with a current injector. Wired-AND connections cause the logic circuit to operate as a NAND logic gate which provides to implement any boolean function. High-speed is achieved by varying the injection current level even at low-voltage supply (<1.5 V) with low-power consumption.     

有界Petri网等价性的判定算法

Petri网语言是系统行为分析的一种重要工具,为了分析有界Petri网的行为等价,借助于有限自动机的等价性问题和算法,研究了有界Petri网的等价性问题和算法.定义了带标注Petri网语言等价性,证明了带标注的有界Petri网到有限自动机的等价转化,给出了判定有界Petri网的等价性算法,为模拟系统的性能比较提供了处理方法.     

多端I/O系统用BiCMOS连线逻辑电路

为了满足数字通信和信息处理系统多端输入/输出(I/O)、高速、低耗的性能要求,笔者设计了几例BiCMOS连线逻辑电路,并提出了采用0.5 mm BiCMOS工艺,制备所设计的连线逻辑电路的技术要点和元器件参数。所做实验表明了设计的连线逻辑电路既具有双极型逻辑门电路快速、大电流驱动能力的特点,又具备CMOS逻辑门低压、低功耗的长处,而且其扇入数可达3~16,扇出数可达1~18,因而它们特别适用于多端I/O高速数字通信和信息处理系统中。     

An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family

This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA taking into account the configurability of such flexible device. The proposed approach concerns the XILINX 4000 family. On this example of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then test configurations for a single logic cell, and finally test configurations for the m × m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a logic cell. An approach for the logic cell of the XILINX4000 family is then described to define a minimum number of test configurations knowing the test configurations of its logic modules. This approach gives only 5 test configurations for the XILINX4000 family while the previous published works concerning Boolean testing of this FPGA family gives 8 or 21 test configurations.     

An Efficient and Accurate DC Analysis Technique for Switched-Capacitor Circuits

A simple but highly accurate method is proposed to find the dc parameters of active or passive switched-capacitor (SC) circuits. It is based on the dc model of a general SC branch.     

An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems

Fast and correct timing verification is a critical issue in VLSIdesign. Several timing verification algorithms have been proposed in thelast few years. However, due to the huge computation time needed toeliminate false paths, existing algorithms have difficulty in performingtiming verification for large circuits. This paper presents efficientcritical path analysis algorithm based on test pattern generation with a newsensitization criterion. The algorithm does not require generation of a pathlist and elimination of false paths to find out the correct critical path ofthe circuit. The inputs which sensitize the critical path are determined aswell. The efficiency and speed of our algorithm are demonstrated using theISCAS benchmark circuits, and the critical paths are found in vastlyimproved times.     

一种基于模糊逻辑的图像增强算法

在分析Pal模糊增强算法不足的基础上，提出了一种改进的模糊增强算法，该算法简化了Pal算法中复杂的变换和逆变换运算，并采用新的增强算子，可根据不同类型的图像动态调整隶属度阅值υc，克服了Pal算法中隶属度阅值设置为固定值的不足，而且减少了迭代次数。实验证明，该算法适用面广，尤其时对于灰度范围相对比较集中的低对比度的医学图像，处理效果更佳。     

An analog behavioral equivalence boundary search methodology for simulink models and circuit level designs utilizing evolutionary computation

We propose a simulation-based analog equivalence boundary search methodology for high level Simulink models and their low level HSpice counterparts.The equivalence of high and low level designs is determined by comparing a set of predefined performance parameters measured during the simulation of both models. Our methodology investigates the search space to obtain boundary of input parameters, where both models have equivalent performance parameters. We build an optimization problem, where the error percentage between the performance parameters of both models being less than a specified threshold is defined as success criteria. In this problem, input parameters are determined by utilizing evolutionary computation. At the end of the optimization, the border of equivalence for the models is found for input parameters satisfying the success criteria. We demonstrate the validity of our approach on three designs, an inverter, an operational amplifier, and a buck converter, where our approach proves to be an efficient tool in finding an equivalence boundary of analog circuits and models.     

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

The objective of this paper is to propose a BIST scheme enabling the test of delay faults in all the Look-Up Tables (LUTs) of FPGA SRAMs, in a Manufacturing context. The BIST scheme does not consume any area overhead and can be removed from the device after the test thus, allowing the use of the whole circuit by the user. The structure we propose is composed of a simple test pattern generator, an error detector and a chain of LUTs. The chain of LUTs is formed alternatively by a LUT and a flip–flop. By using such a chain, the test of all delay faults in every LUT is enabled. In this paper, we develop an experiment based on the implantation of our BIST architecture in a Virtex FPGA from Xilinx. The purpose of this experiment is to show the feasibility of our solution. As a result, one important issue from this solution is its ability to detect the “smallest” delay faults in the LUTs, i.e. the smallest delays that can be observed on a LUT output. Patrick Girard is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Micro-electronics of Montpellier—France). His research interests include the various aspects of digital testing, with special emphasis on DfT, logic BIST, delay fault testing, and low power testing. He has authored and co-authored more than 90 papers on these fields, and has supervised several PhD dissertations. He has also participated to several European research projects (Esprit III ATSEC, Eureka MEDEA, MEDEA+ ASSOCIATE, IST MARLOW). Patrick GIRARD holds a B.Sc. and a M.Sc. in Electrical Engineering, and obtained the Ph.D. degree in microelectronics from the University of Montpellier in 1992. Olivier Héron is presently researcher at CEA (French Center for Technology Research) in the laboratory of Reliability for Embedded Systems. His research interests are Logic BIST, On-Line Testing, Delay Fault Testing of FPGAs and Fault Modelling. He is a member of the program commitee of the Field Programmable Logic Conference FPL2006. He received his Ph.D. from the University of Montpellier (France) in 2004 and worked in the Microelectronics Department of the LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier—France). He received the B.Sc. degree in 1998 and the M.Sc. degree in 2001 in Electrical Engineering from the University of Montpellier. Serge Pravossoudovitch was born in 1957. He is currently Professor in the Electrical and Computer Engineering Department of the University of Montpellier and his research activities are performed at LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier—France). He is received the Master degree in Electrical Engineering in 1979 from the University of Montpellier. He got his Ph.D. degree in Electrical Engineering in 1983 on symbolic layout for IC design. Since 1984, he was been interested in the testing domain. He obtained the “doctorat d’état” degree in 1987 for his works on switch level automatic test pattern generation. He is presently interested in delay fault testing, design for testability and power consumption optimization. He has authored and co-authored numerous papers on these fields and has supervised several Ph.D. dissertations. He has also participated to several European projects (Microelectronic regulation, Esprit, MEDEA). Michel Renovell is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier). His research interests include: Fault modeling, Analog testing and FPGA testing. He is Vice-Chair of the IEEE TTTC (Test Technology Technical Committee) and Chair of the FPGA testing Committee. He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. Michel has been General Chair of several conferences: International Mixed Signal Testing Workshop IMSTW2000, Field Programmable Logic Conference FPL2002 and European Test Symposium ETS2004. A preliminary version of this work has been presented at the 1st European Test Symposium 2004, in Ajaccio.