Electron and hole mobility enhancement in strained-Si MOSFET's onSiGe-on-insulator substrates fabricated by SIMOX technology

We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si_0.9Ge_0.1 layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer     

CMOS on local SOI using SIMOX technology

CMOS on local SOI, in which n-MOS/bulk and p-MOS/SOI can be selectively implemented on the same chip, has been developed. SOI regions are formed by SIMOX technology, while bulk regions are prepared by etching of the buried SiO2. A CMOS inverter fabricated on local SOI shows good transfer characteristics.     

NBTI and hot carrier effect of SOI p-MOSFETs fabricated in strained Si SOI wafer

Comparative study on NBTI and hot carrier effects of p-channel MOSFETs fabricated by using strained SOI wafer and unstrained SOI wafer has been performed, respectively. It is observed that NBTI and hot carrier degradation are more significant in strained SOI devices compared with unstrained SOI devices. Since the devices fabricated in strained SOI wafer are SiGe free strained devices, the more generation of interface states during gate oxidation is the main cause for enhanced NBTI and hot carrier degradation in strained SOI devices.     

Improved BRT structures fabricated using SIMOX technology

The SIMBRT is a new power device in which SIMOX technology is used to isolate the P-channel turnoff MOSFET resulting in improved cathode injection efficiencies and higher maximum controllable current densities when compared to the conventional BRT. In this paper, experimentally measured characteristics on four novel SIMBRT structures fabricated using a 9-mask SIMOX smart power process are presented, and their performance is compared with conventional BRT structures fabricated alongside. The lowest on-state voltage drop and highest maximum controllable current density are demonstrated to occur for the structure with the smallest cell pitch     

Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate

Chemical-mechanical-polishing (CMP) was used to smooth the surface of a SiGe substrate, on which strained-Si n- and p-MOSFETs were fabricated. By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, namely, to 0.4 nm (rms). A strained-Si layer was then successfully grown on the CMP-treated SiGe substrate. The fabricated strained-Si MOSFETs showed good turn-off characteristics, (i.e., equivalent to those of Si control devices). Moreover, capacitance-voltage (CV) measurements revealed that the quality of the gate oxide of the strained-Si devices was the same as that of the Si control devices. Flat-band and threshold voltages of the strained-Si devices were different from those of the Si control devices mainly due to band discontinuity. Electron and hole mobilities of strained-Si MOSFETs under a vertical field up to 1.5 MV/cm increased by 120% and 42%, respectively, compared to the universal mobility. Furthermore, current drive of the n- and p-MOSFETs (L/sub eff//spl ges/0.3 /spl mu/m) was increased roughly by 70% and 50%, respectively. These improvements in characteristics indicate that CMP of the SiGe substrate is a critical technique for developing high-performance strained-Si CMOS.     

Enhanced CMOS performances using substrate strained-SiGe and mechanical strained-Si technology

We developed a novel CMOS architecture that uses mechanical tensile stress, induced by the Si nitride-capping layer, together with the pseudomorphic compressive stress in SiGe layer to improve the drive current of both n- and pMOSFETs simultaneously. The unique advantage of this process flow is that on the same wafer, individual MOSFET performance can be adjusted independently to their optimum due to the separation process for two type devices. It is found that n- and pMOSFETs in the novel CMOS architecture behaved better in performance, not only a higher drain-to-source saturation current but also higher transconductance with wide gate voltage swing, than the Si-control devices, thus making this flow to show a great flexibility for developing next-generation high-performance CMOS.     

SOI/bulk hybrid technology on SIMOX wafers for high performancecircuits with good ESD immunity

A new SOI/bulk hybrid technology with devices on both the thin film and the bottom substrate of SIMOX wafers has been studied. By fabricating ESD protection circuits on the substrate of SIMOX wafers, ESD reliability of high performance CMOS SOI circuits can be significantly improved. Despite the higher surface defect density and micro-roughness on the bottom substrate of SIMOX wafers compared to ordinary bulk wafers, similar electron mobility, intrinsic thermal oxide properties and hot-carrier degradation are observed among MOSFET's fabricated on the different substrates. Thus, the hybrid technology is capable of combining the advantages both of SOI and bulk technology in fabricating high performance circuits     

A stacked CMOS technology on SOI substrate

A stacked CMOS technology fabricated on semiconductor-on-insulator (SOI) wafers with the p-MOSFET on the SOI film and the n-MOSFET on the bulk substrate is demonstrated. The technology provides a number of advantages, including: 1) single crystal multi-layer of active devices; 2) self-aligned double-gate p-MOSFET with thick source/drain and thin channel regions; 3) self-aligned channel region of n-MOSFET to p-MOSFET stacked perfectly on top of each other; 4) significant area saving; and 5) reduced interconnect distance and loading. Experimental results show that the fabricated double-gate p-MOSFET has a nearly ideal subthreshold swing and almost the same current drive as the n-MOSFET with the same lateral width, resulting in a highly compact and completely overlap stacked CMOS inverter.     

Subscriber line interface circuit LSI fabricated using high-voltage CMOS/SIMOX technology

High-voltage buried-channel CMOS/SIMOX technology which is characterised with the existence of an electric-field-shielding layer formed by oxygen implanatation was applied to fabricate a BSH-LSI for a subscriber line interface circuit, providing three functions of battery feed, supervision and hybrid. In this CMOS BSH-LSI, a high breakdown voltage of higher than 60 V and a low breakdown voltage of 15 V were fabricated by the same process. This BSH-LSI showed a high level of performance during operation. The chip size and dissipation power of the BSH-LSI were reduced to approximately one-third and one-half, respectively, compared with a conventional BSH-LSI fabricated with bipolar technology.     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

Ultrafast CMOS inverter with 4.7 ps gate delay fabricated on 90 nm SOI technology

Very low gate delays of 7.7 ps at 1 V supply and 4.7 ps at 2 V supply have been achieved for CMOS inverters fabricated on a 90 nm silicon on insulator technology. The results are measured with an optimised CMOS ring oscillator. These are believed to be the lowest gate delays reported to date for CMOS inverters at room temperature.     

30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is the first drain-pumped transconductance mixer that requires no dc supply power. The monolithic microwave integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator CMOS technology. All impedance matching, bias, and filter elements are implemented on the chip, which has a compact size of 0.5 mm/spl times/0.47 mm. The circuit covers a radio frequency range from 30 to 40 GHz. At a RF frequency of 35 GHz, an intermediate frequency of 2.5 GHz and a local-oscillator (LO) power of 7.5 dBm, a conversion loss of 4.6 dB, a single-sideband (SSB) noise figure (NF) of 7.9 dB, an 1-dB input compression point of -6 dBm, and a third-order intercept point at the input of 2 dBm were measured. At lower LO power of 0 dBm, a conversion loss of 6.3 dBm and an SSB NF of 9.7 dB were measured, making the mixer an excellent candidate for low power-consuming wireless local-area networks. All results include the pad parasitics. To the knowledge of the authors, this is the first CMOS mixer operating at millimeter-wave frequencies. The achieved conversion loss is even lower than for passive MMIC mixers using leading edge III/V technologies, showing the excellent suitability of digital CMOS technology for analog circuits at millimeter-wave frequencies.     

A vertical channel JFET fabricated using silicon planar technology

A vertical channel JFET with a new structure was fabricated using a self-aligned process and doped polysilicon technology. This structure is suitable for a high power device, since many channels are easily integrated on a single chip. It is also suitable for a high frequency device, because two essential conditions for high frequency operation, sufficiently low gate resistance and small channel length, can be realized without difficulty. This device shows triode-like I-V characteristics, which are determined by the channel impurity concentration and gate diffusion profile. Typical performances of an n-channel, 4 mm/spl times/4 mm, 5520 channel power FET, designed for an audio amplifier, are a voltage amplification factor of 5, a source-to-gate breakdown voltage of 60 V, a drain-to-gate breakdown voltage of 200 V, and I/SUB DSS/=4 A at V/SUB DS/=7 V.     

Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate

P-channel dual-gated thin-film silicon-on-insulator (DG-TFSOI) MOSFETs have been fabricated with an isolated buried polysilicon backgate in an SOI island formed by epitaxial lateral overgrowth (ELO) of silicon. This structure allows individual operation of both the top and back gates rather than the conventional common backgate structure. When fully-depleted, the buried gate is used to individually shift the top gate threshold voltage (V/sub T/). A linear shift of /spl Delta/V/sub T,top///spl Delta/V/sub G,back/ of 0.5 V/V was achieved with a thin buried oxide. The effective density of interface traps (D/sub it/) for the backgate polysilicon-oxide SOI interface was measured to be 1.8/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV as compared to the substrate-oxide of 1.1/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV.     

50-nm gate Schottky source/drain p-MOSFETs with a SiGe channel

We propose new SiGe channel p-MOSFETs with germano-silicide Schottky source/drains (S/Ds). The Schottky barrier-height (SBH) for SiGe is expected to be low enough to improve the injection of carriers into the SiGe channel and, as a result, current drivability is also expected to improve. In this work, we demonstrate the proposed Schottky S/D p-MOSFETs down to a 50-nm gate-length. The drain current and transconductance are -339 /spl mu/A//spl mu/m and 285 /spl mu/S//spl mu/m at V/sub GS/=V/sub DS/=-1.5 V, respectively. By increasing the Ge content in the SiGe channel from 30% to 35%, the drive current. and transconductance can be improved up to 23% and 18%, respectively. This is partly due to the lower barrier-height for strained Si/sub 0.65/Ge/sub 0.35/ channel than those for strained Si/sub 0.7/Ge/sub 0.3/ channel device and partly due to the lower effective mass of the holes.     

Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGeheterostructure channel

Thin-body p-channel MOS transistors with a SiGe/Si heterostructure channel were fabricated on silicon-on-insulator (SOI) substrates. A novel lateral solid-phase epitaxy process was employed to form the thin-body for the suppression of short-channel effects. A selective silicon implant that breaks up the interfacial oxide was shown to facilitate unilateral crystallization to form a single crystalline channel. Negligible threshold voltage roll-off was observed down to a gate length of 50 nm. The incorporation of Si_0.7Ge_0.3 in the channel resulted in a 70% enhancement in the drive current. This is the smallest SiGe heterostructure-channel MOS transistor reported to date. This is also the first demonstration of a thin-body MOS transistor incorporating a SiGe heterostructure channel     

A wide range linear variable resistor by buried channel MOS/SIMOX

A low-distortion linear variable resistor using an offset gate buried-channel MOSFET fabricated by SIMOX technology is described. The offset gate structure on the insulating substrate provides 15 to 100 k/spl Omega/ drain-to-source resistance, and 2.5% total harmonic distortion at 100 k/spl Omega/. In a battery-feed circuit application for a subscriber-line interface circuit, the area of a variable conventional polysilicon resistor.     

Investigation of a multigigahertz MOSFET amplifier with an on-chipinductor fabricated on a SIMOX wafer

This paper describes a technology that can be used to integrate multigigahertz RF circuits into large-scale digital circuits. Spiral inductors and a MOSFET amplifier with an inductive load were fabricated on a SIMOX wafer in order to demonstrate the feasibility of SOI technology. With a 1-V supply voltage, peaking of the amplifier gain was observed, as expected from circuit simulations, at 1-4 GHz. These results show that RF circuits with inductors can be implemented on a SIMOX wafer by using the conventional digital CMOS LSI process     

Temperature behavior of spiral inductors on high resistivity substrate in SOI CMOS technology

This paper reviews and analyzes a compact model for integrated planar spiral inductors on standard and high resistivity substrates in silicon-on-insulator (SOI) technology. The inductors have been characterized over a temperature range from 25 to 200 °C. The temperature variation of each model parameter has been investigated. It demonstrates that only the variations of the metallic losses versus temperature have to be taken into account to model properly the high frequency behavior over a wide temperature range of a spiral inductor integrated on silicon high resistivity substrate. Based on these experimental and characterization results, guidelines for practical inductor designs in RFICs for high-temperature applications are drawn.